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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s3 4declare <256 x i32> @llvm.vp.srem.v256i32(<256 x i32>, <256 x i32>, <256 x i1>, i32)5 6define fastcc <256 x i32> @test_vp_srem_v256i32_vv(<256 x i32> %i0, <256 x i32> %i1, <256 x i1> %m, i32 %n) {7; CHECK-LABEL: test_vp_srem_v256i32_vv:8; CHECK: # %bb.0:9; CHECK-NEXT: and %s0, %s0, (32)010; CHECK-NEXT: lvl %s011; CHECK-NEXT: vdivs.w.sx %v2, %v0, %v1, %vm112; CHECK-NEXT: vmuls.w.sx %v1, %v1, %v2, %vm113; CHECK-NEXT: vsubs.w.sx %v0, %v0, %v1, %vm114; CHECK-NEXT: b.l.t (, %s10)15 %r0 = call <256 x i32> @llvm.vp.srem.v256i32(<256 x i32> %i0, <256 x i32> %i1, <256 x i1> %m, i32 %n)16 ret <256 x i32> %r017}18 19define fastcc <256 x i32> @test_vp_srem_v256i32_rv(i32 %s0, <256 x i32> %i1, <256 x i1> %m, i32 %n) {20; CHECK-LABEL: test_vp_srem_v256i32_rv:21; CHECK: # %bb.0:22; CHECK-NEXT: and %s1, %s1, (32)023; CHECK-NEXT: and %s0, %s0, (32)024; CHECK-NEXT: lvl %s125; CHECK-NEXT: vdivs.w.sx %v1, %s0, %v0, %vm126; CHECK-NEXT: vmuls.w.sx %v0, %v0, %v1, %vm127; CHECK-NEXT: vsubs.w.sx %v0, %s0, %v0, %vm128; CHECK-NEXT: b.l.t (, %s10)29 %xins = insertelement <256 x i32> undef, i32 %s0, i32 030 %i0 = shufflevector <256 x i32> %xins, <256 x i32> undef, <256 x i32> zeroinitializer31 %r0 = call <256 x i32> @llvm.vp.srem.v256i32(<256 x i32> %i0, <256 x i32> %i1, <256 x i1> %m, i32 %n)32 ret <256 x i32> %r033}34 35define fastcc <256 x i32> @test_vp_srem_v256i32_vr(<256 x i32> %i0, i32 %s1, <256 x i1> %m, i32 %n) {36; CHECK-LABEL: test_vp_srem_v256i32_vr:37; CHECK: # %bb.0:38; CHECK-NEXT: and %s1, %s1, (32)039; CHECK-NEXT: and %s0, %s0, (32)040; CHECK-NEXT: lvl %s141; CHECK-NEXT: vdivs.w.sx %v1, %v0, %s0, %vm142; CHECK-NEXT: vmuls.w.sx %v1, %s0, %v1, %vm143; CHECK-NEXT: vsubs.w.sx %v0, %v0, %v1, %vm144; CHECK-NEXT: b.l.t (, %s10)45 %yins = insertelement <256 x i32> undef, i32 %s1, i32 046 %i1 = shufflevector <256 x i32> %yins, <256 x i32> undef, <256 x i32> zeroinitializer47 %r0 = call <256 x i32> @llvm.vp.srem.v256i32(<256 x i32> %i0, <256 x i32> %i1, <256 x i1> %m, i32 %n)48 ret <256 x i32> %r049}50 51 52declare <256 x i64> @llvm.vp.srem.v256i64(<256 x i64>, <256 x i64>, <256 x i1>, i32)53 54define fastcc <256 x i64> @test_vp_int_v256i64_vv(<256 x i64> %i0, <256 x i64> %i1, <256 x i1> %m, i32 %n) {55; CHECK-LABEL: test_vp_int_v256i64_vv:56; CHECK: # %bb.0:57; CHECK-NEXT: and %s0, %s0, (32)058; CHECK-NEXT: lvl %s059; CHECK-NEXT: vdivs.l %v2, %v0, %v1, %vm160; CHECK-NEXT: vmuls.l %v1, %v1, %v2, %vm161; CHECK-NEXT: vsubs.l %v0, %v0, %v1, %vm162; CHECK-NEXT: b.l.t (, %s10)63 %r0 = call <256 x i64> @llvm.vp.srem.v256i64(<256 x i64> %i0, <256 x i64> %i1, <256 x i1> %m, i32 %n)64 ret <256 x i64> %r065}66 67define fastcc <256 x i64> @test_vp_srem_v256i64_rv(i64 %s0, <256 x i64> %i1, <256 x i1> %m, i32 %n) {68; CHECK-LABEL: test_vp_srem_v256i64_rv:69; CHECK: # %bb.0:70; CHECK-NEXT: and %s1, %s1, (32)071; CHECK-NEXT: lvl %s172; CHECK-NEXT: vdivs.l %v1, %s0, %v0, %vm173; CHECK-NEXT: vmuls.l %v0, %v0, %v1, %vm174; CHECK-NEXT: vsubs.l %v0, %s0, %v0, %vm175; CHECK-NEXT: b.l.t (, %s10)76 %xins = insertelement <256 x i64> undef, i64 %s0, i32 077 %i0 = shufflevector <256 x i64> %xins, <256 x i64> undef, <256 x i32> zeroinitializer78 %r0 = call <256 x i64> @llvm.vp.srem.v256i64(<256 x i64> %i0, <256 x i64> %i1, <256 x i1> %m, i32 %n)79 ret <256 x i64> %r080}81 82define fastcc <256 x i64> @test_vp_srem_v256i64_vr(<256 x i64> %i0, i64 %s1, <256 x i1> %m, i32 %n) {83; CHECK-LABEL: test_vp_srem_v256i64_vr:84; CHECK: # %bb.0:85; CHECK-NEXT: and %s1, %s1, (32)086; CHECK-NEXT: lvl %s187; CHECK-NEXT: vdivs.l %v1, %v0, %s0, %vm188; CHECK-NEXT: vmuls.l %v1, %s0, %v1, %vm189; CHECK-NEXT: vsubs.l %v0, %v0, %v1, %vm190; CHECK-NEXT: b.l.t (, %s10)91 %yins = insertelement <256 x i64> undef, i64 %s1, i32 092 %i1 = shufflevector <256 x i64> %yins, <256 x i64> undef, <256 x i32> zeroinitializer93 %r0 = call <256 x i64> @llvm.vp.srem.v256i64(<256 x i64> %i0, <256 x i64> %i1, <256 x i1> %m, i32 %n)94 ret <256 x i64> %r095}96