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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=ve-unknown-unknown -mattr=+vpu | FileCheck %s3 4declare <256 x float> @llvm.experimental.vp.strided.load.v256f32.p0.i64(ptr %ptr, i64 %stride, <256 x i1> %mask, i32 %evl)5 6define fastcc <256 x float> @vp_strided_load_v256f32_rrm(ptr %ptr, i64 %stride, <256 x i1> %mask, i32 %evl) {7; CHECK-LABEL: vp_strided_load_v256f32_rrm:8; CHECK: # %bb.0:9; CHECK-NEXT: and %s2, %s2, (32)010; CHECK-NEXT: lvl %s211; CHECK-NEXT: vseq %v012; CHECK-NEXT: vmulu.l %v0, %s1, %v0, %vm113; CHECK-NEXT: vaddu.l %v0, %s0, %v0, %vm114; CHECK-NEXT: vgtu %v0, %v0, 0, 0, %vm115; CHECK-NEXT: b.l.t (, %s10)16 %r = call <256 x float> @llvm.experimental.vp.strided.load.v256f32.p0.i64(ptr %ptr, i64 %stride, <256 x i1> %mask, i32 %evl)17 ret <256 x float> %r18}19 20define fastcc <256 x float> @vp_strided_load_v256f32_rr(ptr %ptr, i64 %stride, i32 %evl) {21; CHECK-LABEL: vp_strided_load_v256f32_rr:22; CHECK: # %bb.0:23; CHECK-NEXT: and %s2, %s2, (32)024; CHECK-NEXT: lvl %s225; CHECK-NEXT: vldu %v0, %s1, %s026; CHECK-NEXT: b.l.t (, %s10)27 %one = insertelement <256 x i1> undef, i1 1, i32 028 %allones = shufflevector <256 x i1> %one, <256 x i1> undef, <256 x i32> zeroinitializer29 %r = call <256 x float> @llvm.experimental.vp.strided.load.v256f32.p0.i64(ptr %ptr, i64 %stride, <256 x i1> %allones, i32 %evl)30 ret <256 x float> %r31}32 33define fastcc <256 x float> @vp_strided_load_v256f32_ri(ptr %ptr, i32 %evl) {34; CHECK-LABEL: vp_strided_load_v256f32_ri:35; CHECK: # %bb.0:36; CHECK-NEXT: and %s1, %s1, (32)037; CHECK-NEXT: lvl %s138; CHECK-NEXT: vldu %v0, 24, %s039; CHECK-NEXT: b.l.t (, %s10)40 %one = insertelement <256 x i1> undef, i1 1, i32 041 %allones = shufflevector <256 x i1> %one, <256 x i1> undef, <256 x i32> zeroinitializer42 %r = call <256 x float> @llvm.experimental.vp.strided.load.v256f32.p0.i64(ptr %ptr, i64 24, <256 x i1> %allones, i32 %evl)43 ret <256 x float> %r44}45 46declare <256 x i32> @llvm.experimental.vp.strided.load.v256i32.p0.i64(ptr %ptr, i64 %stride, <256 x i1> %mask, i32 %evl)47 48define fastcc <256 x i32> @vp_strided_load_v256i32_rrm(ptr %ptr, i64 %stride, <256 x i1> %mask, i32 %evl) {49; CHECK-LABEL: vp_strided_load_v256i32_rrm:50; CHECK: # %bb.0:51; CHECK-NEXT: and %s2, %s2, (32)052; CHECK-NEXT: lvl %s253; CHECK-NEXT: vseq %v054; CHECK-NEXT: vmulu.l %v0, %s1, %v0, %vm155; CHECK-NEXT: vaddu.l %v0, %s0, %v0, %vm156; CHECK-NEXT: vgtl.zx %v0, %v0, 0, 0, %vm157; CHECK-NEXT: b.l.t (, %s10)58 %r = call <256 x i32> @llvm.experimental.vp.strided.load.v256i32.p0.i64(ptr %ptr, i64 %stride, <256 x i1> %mask, i32 %evl)59 ret <256 x i32> %r60}61 62define fastcc <256 x i32> @vp_strided_load_v256i32_rr(ptr %ptr, i64 %stride, i32 %evl) {63; CHECK-LABEL: vp_strided_load_v256i32_rr:64; CHECK: # %bb.0:65; CHECK-NEXT: and %s2, %s2, (32)066; CHECK-NEXT: lvl %s267; CHECK-NEXT: vldl.zx %v0, %s1, %s068; CHECK-NEXT: b.l.t (, %s10)69 %one = insertelement <256 x i1> undef, i1 1, i32 070 %allones = shufflevector <256 x i1> %one, <256 x i1> undef, <256 x i32> zeroinitializer71 %r = call <256 x i32> @llvm.experimental.vp.strided.load.v256i32.p0.i64(ptr %ptr, i64 %stride, <256 x i1> %allones, i32 %evl)72 ret <256 x i32> %r73}74 75define fastcc <256 x i32> @vp_strided_load_v256i32_ri(ptr %ptr, i32 %evl) {76; CHECK-LABEL: vp_strided_load_v256i32_ri:77; CHECK: # %bb.0:78; CHECK-NEXT: and %s1, %s1, (32)079; CHECK-NEXT: lvl %s180; CHECK-NEXT: vldl.zx %v0, 24, %s081; CHECK-NEXT: b.l.t (, %s10)82 %one = insertelement <256 x i1> undef, i1 1, i32 083 %allones = shufflevector <256 x i1> %one, <256 x i1> undef, <256 x i32> zeroinitializer84 %r = call <256 x i32> @llvm.experimental.vp.strided.load.v256i32.p0.i64(ptr %ptr, i64 24, <256 x i1> %allones, i32 %evl)85 ret <256 x i32> %r86}87 88declare <256 x double> @llvm.experimental.vp.strided.load.v256f64.p0.i64(ptr %ptr, i64 %stride, <256 x i1> %mask, i32 %evl)89 90define fastcc <256 x double> @vp_strided_load_v256f64_rrm(ptr %ptr, i64 %stride, <256 x i1> %mask, i32 %evl) {91; CHECK-LABEL: vp_strided_load_v256f64_rrm:92; CHECK: # %bb.0:93; CHECK-NEXT: and %s2, %s2, (32)094; CHECK-NEXT: lvl %s295; CHECK-NEXT: vseq %v096; CHECK-NEXT: vmulu.l %v0, %s1, %v0, %vm197; CHECK-NEXT: vaddu.l %v0, %s0, %v0, %vm198; CHECK-NEXT: vgt %v0, %v0, 0, 0, %vm199; CHECK-NEXT: b.l.t (, %s10)100 %r = call <256 x double> @llvm.experimental.vp.strided.load.v256f64.p0.i64(ptr %ptr, i64 %stride, <256 x i1> %mask, i32 %evl)101 ret <256 x double> %r102}103 104define fastcc <256 x double> @vp_strided_load_v256f64_rr(ptr %ptr, i64 %stride, i32 %evl) {105; CHECK-LABEL: vp_strided_load_v256f64_rr:106; CHECK: # %bb.0:107; CHECK-NEXT: and %s2, %s2, (32)0108; CHECK-NEXT: lvl %s2109; CHECK-NEXT: vld %v0, %s1, %s0110; CHECK-NEXT: b.l.t (, %s10)111 %one = insertelement <256 x i1> undef, i1 1, i32 0112 %allones = shufflevector <256 x i1> %one, <256 x i1> undef, <256 x i32> zeroinitializer113 %r = call <256 x double> @llvm.experimental.vp.strided.load.v256f64.p0.i64(ptr %ptr, i64 %stride, <256 x i1> %allones, i32 %evl)114 ret <256 x double> %r115}116 117define fastcc <256 x double> @vp_strided_load_v256f64_ri(ptr %ptr, i32 %evl) {118; CHECK-LABEL: vp_strided_load_v256f64_ri:119; CHECK: # %bb.0:120; CHECK-NEXT: and %s1, %s1, (32)0121; CHECK-NEXT: lvl %s1122; CHECK-NEXT: vld %v0, 24, %s0123; CHECK-NEXT: b.l.t (, %s10)124 %one = insertelement <256 x i1> undef, i1 1, i32 0125 %allones = shufflevector <256 x i1> %one, <256 x i1> undef, <256 x i32> zeroinitializer126 %r = call <256 x double> @llvm.experimental.vp.strided.load.v256f64.p0.i64(ptr %ptr, i64 24, <256 x i1> %allones, i32 %evl)127 ret <256 x double> %r128}129 130declare <256 x i64> @llvm.experimental.vp.strided.load.v256i64.p0.i64(ptr %ptr, i64 %stride, <256 x i1> %mask, i32 %evl)131 132define fastcc <256 x i64> @vp_strided_load_v256i64_rrm(ptr %ptr, i64 %stride, <256 x i1> %mask, i32 %evl) {133; CHECK-LABEL: vp_strided_load_v256i64_rrm:134; CHECK: # %bb.0:135; CHECK-NEXT: and %s2, %s2, (32)0136; CHECK-NEXT: lvl %s2137; CHECK-NEXT: vseq %v0138; CHECK-NEXT: vmulu.l %v0, %s1, %v0, %vm1139; CHECK-NEXT: vaddu.l %v0, %s0, %v0, %vm1140; CHECK-NEXT: vgt %v0, %v0, 0, 0, %vm1141; CHECK-NEXT: b.l.t (, %s10)142 %r = call <256 x i64> @llvm.experimental.vp.strided.load.v256i64.p0.i64(ptr %ptr, i64 %stride, <256 x i1> %mask, i32 %evl)143 ret <256 x i64> %r144}145 146define fastcc <256 x i64> @vp_strided_load_v256i64_rr(ptr %ptr, i64 %stride, i32 %evl) {147; CHECK-LABEL: vp_strided_load_v256i64_rr:148; CHECK: # %bb.0:149; CHECK-NEXT: and %s2, %s2, (32)0150; CHECK-NEXT: lvl %s2151; CHECK-NEXT: vld %v0, %s1, %s0152; CHECK-NEXT: b.l.t (, %s10)153 %one = insertelement <256 x i1> undef, i1 1, i32 0154 %allones = shufflevector <256 x i1> %one, <256 x i1> undef, <256 x i32> zeroinitializer155 %r = call <256 x i64> @llvm.experimental.vp.strided.load.v256i64.p0.i64(ptr %ptr, i64 %stride, <256 x i1> %allones, i32 %evl)156 ret <256 x i64> %r157}158 159define fastcc <256 x i64> @vp_strided_load_v256i64_ri(ptr %ptr, i32 %evl) {160; CHECK-LABEL: vp_strided_load_v256i64_ri:161; CHECK: # %bb.0:162; CHECK-NEXT: and %s1, %s1, (32)0163; CHECK-NEXT: lvl %s1164; CHECK-NEXT: vld %v0, 24, %s0165; CHECK-NEXT: b.l.t (, %s10)166 %one = insertelement <256 x i1> undef, i1 1, i32 0167 %allones = shufflevector <256 x i1> %one, <256 x i1> undef, <256 x i32> zeroinitializer168 %r = call <256 x i64> @llvm.experimental.vp.strided.load.v256i64.p0.i64(ptr %ptr, i64 24, <256 x i1> %allones, i32 %evl)169 ret <256 x i64> %r170}171