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1; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers | FileCheck %s2 3; This tests that indirectbr instructions are lowered to switches. Currently we4; just re-use the IndirectBrExpand Pass; it has its own IR-level test.5; So this test just ensures that the pass gets run and we can lower indirectbr6 7target triple = "wasm32"8 9@test1.targets = constant [4 x ptr] [ptr blockaddress(@test1, %bb0),10 ptr blockaddress(@test1, %bb1),11 ptr blockaddress(@test1, %bb2),12 ptr blockaddress(@test1, %bb3)]13 14; Just check the barest skeleton of the structure15; CHECK-LABEL: test1:16; CHECK: i32.load17; CHECK: i32.load18; CHECK: loop19; CHECK: block20; CHECK: block21; CHECK: block22; CHECK: block23; CHECK: br_table ${{[^,]+}}, 1, 2, 024; CHECK: end_block25; CHECK: end_block26; CHECK: end_block27; CHECK: end_block28; CHECK: br29; CHECK: end_loop30; CHECK: end_function31; CHECK: test1.targets:32; CHECK-NEXT: .int3233; CHECK-NEXT: .int3234; CHECK-NEXT: .int3235; CHECK-NEXT: .int3236 37define void @test1(ptr readonly %p, ptr %sink) #0 {38 39entry:40 %i0 = load i32, ptr %p41 %target.i0 = getelementptr [4 x ptr], ptr @test1.targets, i32 0, i32 %i042 %target0 = load ptr, ptr %target.i043 ; Only a subset of blocks are viable successors here.44 indirectbr ptr %target0, [label %bb0, label %bb1]45 46 47bb0:48 store volatile i32 0, ptr %sink49 br label %latch50 51bb1:52 store volatile i32 1, ptr %sink53 br label %latch54 55bb2:56 store volatile i32 2, ptr %sink57 br label %latch58 59bb3:60 store volatile i32 3, ptr %sink61 br label %latch62 63latch:64 %i.next = load i32, ptr %p65 %target.i.next = getelementptr [4 x ptr], ptr @test1.targets, i32 0, i32 %i.next66 %target.next = load ptr, ptr %target.i.next67 ; A different subset of blocks are viable successors here.68 indirectbr ptr %target.next, [label %bb1, label %bb2]69}70