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1; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-keep-registers -wasm-disable-explicit-locals -mattr=+simd128 | FileCheck %s --check-prefixes CHECK,SIMD1282; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-keep-registers -wasm-disable-explicit-locals | FileCheck %s --check-prefixes CHECK,NO-SIMD1283 4; Test that bitcasts between vector types are lowered to zero instructions5 6target triple = "wasm32-unknown-unknown"7 8; CHECK-LABEL: v16i8_to_v16i8:9; NO-SIMD128-NOT: return $010; SIMD128: return $011define <16 x i8> @v16i8_to_v16i8(<16 x i8> %v) {12 %res = bitcast <16 x i8> %v to <16 x i8>13 ret <16 x i8> %res14}15 16; CHECK-LABEL: v16i8_to_v8i16:17; NO-SIMD128-NOT: return $018; SIMD128: return $019define <8 x i16> @v16i8_to_v8i16(<16 x i8> %v) {20 %res = bitcast <16 x i8> %v to <8 x i16>21 ret <8 x i16> %res22}23 24; CHECK-LABEL: v16i8_to_v4i32:25; NO-SIMD128-NOT: return $026; SIMD128: return $027define <4 x i32> @v16i8_to_v4i32(<16 x i8> %v) {28 %res = bitcast <16 x i8> %v to <4 x i32>29 ret <4 x i32> %res30}31 32; CHECK-LABEL: v16i8_to_v2i64:33; NO-SIMD128-NOT: return $034; SIMD128: return $035define <2 x i64> @v16i8_to_v2i64(<16 x i8> %v) {36 %res = bitcast <16 x i8> %v to <2 x i64>37 ret <2 x i64> %res38}39 40; CHECK-LABEL: v16i8_to_v4f32:41; NO-SIMD128-NOT: return $042; SIMD128: return $043define <4 x float> @v16i8_to_v4f32(<16 x i8> %v) {44 %res = bitcast <16 x i8> %v to <4 x float>45 ret <4 x float> %res46}47 48; CHECK-LABEL: v16i8_to_v2f64:49; NO-SIMD128-NOT: return $050; SIMD128: return $051define <2 x double> @v16i8_to_v2f64(<16 x i8> %v) {52 %res = bitcast <16 x i8> %v to <2 x double>53 ret <2 x double> %res54}55 56; CHECK-LABEL: v8i16_to_v16i8:57; NO-SIMD128-NOT: return $058; SIMD128: return $059define <16 x i8> @v8i16_to_v16i8(<8 x i16> %v) {60 %res = bitcast <8 x i16> %v to <16 x i8>61 ret <16 x i8> %res62}63 64; CHECK-LABEL: v8i16_to_v8i16:65; NO-SIMD128-NOT: return $066; SIMD128: return $067define <8 x i16> @v8i16_to_v8i16(<8 x i16> %v) {68 %res = bitcast <8 x i16> %v to <8 x i16>69 ret <8 x i16> %res70}71 72; CHECK-LABEL: v8i16_to_v4i32:73; NO-SIMD128-NOT: return $074; SIMD128: return $075define <4 x i32> @v8i16_to_v4i32(<8 x i16> %v) {76 %res = bitcast <8 x i16> %v to <4 x i32>77 ret <4 x i32> %res78}79 80; CHECK-LABEL: v8i16_to_v2i64:81; NO-SIMD128-NOT: return $082; SIMD128: return $083define <2 x i64> @v8i16_to_v2i64(<8 x i16> %v) {84 %res = bitcast <8 x i16> %v to <2 x i64>85 ret <2 x i64> %res86}87 88; CHECK-LABEL: v8i16_to_v4f32:89; NO-SIMD128-NOT: return $090; SIMD128: return $091define <4 x float> @v8i16_to_v4f32(<8 x i16> %v) {92 %res = bitcast <8 x i16> %v to <4 x float>93 ret <4 x float> %res94}95 96; CHECK-LABEL: v8i16_to_v2f64:97; NO-SIMD128-NOT: return $098; SIMD128: return $099define <2 x double> @v8i16_to_v2f64(<8 x i16> %v) {100 %res = bitcast <8 x i16> %v to <2 x double>101 ret <2 x double> %res102}103 104; CHECK-LABEL: v4i32_to_v16i8:105; NO-SIMD128-NOT: return $0106; SIMD128: return $0107define <16 x i8> @v4i32_to_v16i8(<4 x i32> %v) {108 %res = bitcast <4 x i32> %v to <16 x i8>109 ret <16 x i8> %res110}111 112; CHECK-LABEL: v4i32_to_v8i16:113; NO-SIMD128-NOT: return $0114; SIMD128: return $0115define <8 x i16> @v4i32_to_v8i16(<4 x i32> %v) {116 %res = bitcast <4 x i32> %v to <8 x i16>117 ret <8 x i16> %res118}119 120; CHECK-LABEL: v4i32_to_v4i32:121; NO-SIMD128-NOT: return $0122; SIMD128: return $0123define <4 x i32> @v4i32_to_v4i32(<4 x i32> %v) {124 %res = bitcast <4 x i32> %v to <4 x i32>125 ret <4 x i32> %res126}127 128; CHECK-LABEL: v4i32_to_v2i64:129; NO-SIMD128-NOT: return $0130; SIMD128: return $0131define <2 x i64> @v4i32_to_v2i64(<4 x i32> %v) {132 %res = bitcast <4 x i32> %v to <2 x i64>133 ret <2 x i64> %res134}135 136; CHECK-LABEL: v4i32_to_v4f32:137; NO-SIMD128-NOT: return $0138; SIMD128: return $0139define <4 x float> @v4i32_to_v4f32(<4 x i32> %v) {140 %res = bitcast <4 x i32> %v to <4 x float>141 ret <4 x float> %res142}143 144; CHECK-LABEL: v4i32_to_v2f64:145; NO-SIMD128-NOT: return $0146; SIMD128: return $0147define <2 x double> @v4i32_to_v2f64(<4 x i32> %v) {148 %res = bitcast <4 x i32> %v to <2 x double>149 ret <2 x double> %res150}151 152; CHECK-LABEL: v2i64_to_v16i8:153; NO-SIMD128-NOT: return $0154; SIMD128: return $0155define <16 x i8> @v2i64_to_v16i8(<2 x i64> %v) {156 %res = bitcast <2 x i64> %v to <16 x i8>157 ret <16 x i8> %res158}159 160; CHECK-LABEL: v2i64_to_v8i16:161; NO-SIMD128-NOT: return $0162; SIMD128: return $0163define <8 x i16> @v2i64_to_v8i16(<2 x i64> %v) {164 %res = bitcast <2 x i64> %v to <8 x i16>165 ret <8 x i16> %res166}167 168; CHECK-LABEL: v2i64_to_v4i32:169; NO-SIMD128-NOT: return $0170; SIMD128: return $0171define <4 x i32> @v2i64_to_v4i32(<2 x i64> %v) {172 %res = bitcast <2 x i64> %v to <4 x i32>173 ret <4 x i32> %res174}175 176; CHECK-LABEL: v2i64_to_v2i64:177; NO-SIMD128-NOT: return $0178; SIMD128: return $0179define <2 x i64> @v2i64_to_v2i64(<2 x i64> %v) {180 %res = bitcast <2 x i64> %v to <2 x i64>181 ret <2 x i64> %res182}183 184; CHECK-LABEL: v2i64_to_v4f32:185; NO-SIMD128-NOT: return $0186; SIMD128: return $0187define <4 x float> @v2i64_to_v4f32(<2 x i64> %v) {188 %res = bitcast <2 x i64> %v to <4 x float>189 ret <4 x float> %res190}191 192; CHECK-LABEL: v2i64_to_v2f64:193; NO-SIMD128-NOT: return $0194; SIMD128: return $0195define <2 x double> @v2i64_to_v2f64(<2 x i64> %v) {196 %res = bitcast <2 x i64> %v to <2 x double>197 ret <2 x double> %res198}199 200; CHECK-LABEL: v4f32_to_v16i8:201; NO-SIMD128-NOT: return $0202; SIMD128: return $0203define <16 x i8> @v4f32_to_v16i8(<4 x float> %v) {204 %res = bitcast <4 x float> %v to <16 x i8>205 ret <16 x i8> %res206}207 208; CHECK-LABEL: v4f32_to_v8i16:209; NO-SIMD128-NOT: return $0210; SIMD128: return $0211define <8 x i16> @v4f32_to_v8i16(<4 x float> %v) {212 %res = bitcast <4 x float> %v to <8 x i16>213 ret <8 x i16> %res214}215 216; CHECK-LABEL: v4f32_to_v4i32:217; NO-SIMD128-NOT: return $0218; SIMD128: return $0219define <4 x i32> @v4f32_to_v4i32(<4 x float> %v) {220 %res = bitcast <4 x float> %v to <4 x i32>221 ret <4 x i32> %res222}223 224; CHECK-LABEL: v4f32_to_v2i64:225; NO-SIMD128-NOT: return $0226; SIMD128: return $0227define <2 x i64> @v4f32_to_v2i64(<4 x float> %v) {228 %res = bitcast <4 x float> %v to <2 x i64>229 ret <2 x i64> %res230}231 232; CHECK-LABEL: v4f32_to_v4f32:233; NO-SIMD128-NOT: return $0234; SIMD128: return $0235define <4 x float> @v4f32_to_v4f32(<4 x float> %v) {236 %res = bitcast <4 x float> %v to <4 x float>237 ret <4 x float> %res238}239 240; CHECK-LABEL: v4f32_to_v2f64:241; NO-SIMD128-NOT: return $0242; SIMD128: return $0243define <2 x double> @v4f32_to_v2f64(<4 x float> %v) {244 %res = bitcast <4 x float> %v to <2 x double>245 ret <2 x double> %res246}247 248; CHECK-LABEL: v2f64_to_v16i8:249; NO-SIMD128-NOT: return $0250; SIMD128: return $0251define <16 x i8> @v2f64_to_v16i8(<2 x double> %v) {252 %res = bitcast <2 x double> %v to <16 x i8>253 ret <16 x i8> %res254}255 256; CHECK-LABEL: v2f64_to_v8i16:257; NO-SIMD128-NOT: return $0258; SIMD128: return $0259define <8 x i16> @v2f64_to_v8i16(<2 x double> %v) {260 %res = bitcast <2 x double> %v to <8 x i16>261 ret <8 x i16> %res262}263 264; CHECK-LABEL: v2f64_to_v4i32:265; NO-SIMD128-NOT: return $0266; SIMD128: return $0267define <4 x i32> @v2f64_to_v4i32(<2 x double> %v) {268 %res = bitcast <2 x double> %v to <4 x i32>269 ret <4 x i32> %res270}271 272; CHECK-LABEL: v2f64_to_v2i64:273; NO-SIMD128-NOT: return $0274; SIMD128: return $0275define <2 x i64> @v2f64_to_v2i64(<2 x double> %v) {276 %res = bitcast <2 x double> %v to <2 x i64>277 ret <2 x i64> %res278}279 280; CHECK-LABEL: v2f64_to_v4f32:281; NO-SIMD128-NOT: return $0282; SIMD128: return $0283define <4 x float> @v2f64_to_v4f32(<2 x double> %v) {284 %res = bitcast <2 x double> %v to <4 x float>285 ret <4 x float> %res286}287 288; CHECK-LABEL: v2f64_to_v2f64:289; NO-SIMD128-NOT: return $0290; SIMD128: return $0291define <2 x double> @v2f64_to_v2f64(<2 x double> %v) {292 %res = bitcast <2 x double> %v to <2 x double>293 ret <2 x double> %res294}295