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1; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128,+relaxed-simd | FileCheck %s --check-prefixes=CHECK,SLOW2; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128,+relaxed-simd -fast-isel | FileCheck %s3 4; Test that SIMD128 intrinsics lower as expected. These intrinsics are5; only expected to lower successfully if the simd128 attribute is6; enabled and legal types are used.7 8target triple = "wasm32-unknown-unknown"9 10; ==============================================================================11; 16 x i812; ==============================================================================13; CHECK-LABEL: swizzle_v16i8:14; CHECK-NEXT: .functype swizzle_v16i8 (v128, v128) -> (v128){{$}}15; CHECK-NEXT: i8x16.swizzle $push[[R:[0-9]+]]=, $0, $1{{$}}16; CHECK-NEXT: return $pop[[R]]{{$}}17declare <16 x i8> @llvm.wasm.swizzle(<16 x i8>, <16 x i8>)18define <16 x i8> @swizzle_v16i8(<16 x i8> %x, <16 x i8> %y) {19 %a = call <16 x i8> @llvm.wasm.swizzle(<16 x i8> %x, <16 x i8> %y)20 ret <16 x i8> %a21}22 23; CHECK-LABEL: add_sat_s_v16i8:24; CHECK-NEXT: .functype add_sat_s_v16i8 (v128, v128) -> (v128){{$}}25; CHECK-NEXT: i8x16.add_sat_s $push[[R:[0-9]+]]=, $0, $1{{$}}26; CHECK-NEXT: return $pop[[R]]{{$}}27declare <16 x i8> @llvm.sadd.sat.v16i8(<16 x i8>, <16 x i8>)28define <16 x i8> @add_sat_s_v16i8(<16 x i8> %x, <16 x i8> %y) {29 %a = call <16 x i8> @llvm.sadd.sat.v16i8(<16 x i8> %x, <16 x i8> %y)30 ret <16 x i8> %a31}32 33; CHECK-LABEL: add_sat_u_v16i8:34; CHECK-NEXT: .functype add_sat_u_v16i8 (v128, v128) -> (v128){{$}}35; CHECK-NEXT: i8x16.add_sat_u $push[[R:[0-9]+]]=, $0, $1{{$}}36; CHECK-NEXT: return $pop[[R]]{{$}}37declare <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8>, <16 x i8>)38define <16 x i8> @add_sat_u_v16i8(<16 x i8> %x, <16 x i8> %y) {39 %a = call <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8> %x, <16 x i8> %y)40 ret <16 x i8> %a41}42 43; CHECK-LABEL: sub_sat_s_v16i8:44; CHECK-NEXT: .functype sub_sat_s_v16i8 (v128, v128) -> (v128){{$}}45; CHECK-NEXT: i8x16.sub_sat_s $push[[R:[0-9]+]]=, $0, $1{{$}}46; CHECK-NEXT: return $pop[[R]]{{$}}47declare <16 x i8> @llvm.ssub.sat.v16i8(<16 x i8>, <16 x i8>)48define <16 x i8> @sub_sat_s_v16i8(<16 x i8> %x, <16 x i8> %y) {49 %a = call <16 x i8> @llvm.ssub.sat.v16i8(50 <16 x i8> %x, <16 x i8> %y51 )52 ret <16 x i8> %a53}54 55; CHECK-LABEL: sub_sat_u_v16i8:56; CHECK-NEXT: .functype sub_sat_u_v16i8 (v128, v128) -> (v128){{$}}57; CHECK-NEXT: i8x16.sub_sat_u $push[[R:[0-9]+]]=, $0, $1{{$}}58; CHECK-NEXT: return $pop[[R]]{{$}}59declare <16 x i8> @llvm.usub.sat.v16i8(<16 x i8>, <16 x i8>)60define <16 x i8> @sub_sat_u_v16i8(<16 x i8> %x, <16 x i8> %y) {61 %a = call <16 x i8> @llvm.usub.sat.v16i8(62 <16 x i8> %x, <16 x i8> %y63 )64 ret <16 x i8> %a65}66 67; CHECK-LABEL: avgr_u_v16i8:68; CHECK-NEXT: .functype avgr_u_v16i8 (v128, v128) -> (v128){{$}}69; CHECK-NEXT: i8x16.avgr_u $push[[R:[0-9]+]]=, $0, $1{{$}}70; CHECK-NEXT: return $pop[[R]]{{$}}71declare <16 x i8> @llvm.wasm.avgr.unsigned.v16i8(<16 x i8>, <16 x i8>)72define <16 x i8> @avgr_u_v16i8(<16 x i8> %x, <16 x i8> %y) {73 %a = call <16 x i8> @llvm.wasm.avgr.unsigned.v16i8(<16 x i8> %x, <16 x i8> %y)74 ret <16 x i8> %a75}76 77; CHECK-LABEL: popcnt_v16i8:78; CHECK-NEXT: .functype popcnt_v16i8 (v128) -> (v128){{$}}79; CHECK-NEXT: i8x16.popcnt $push[[R:[0-9]+]]=, $0{{$}}80; CHECK-NEXT: return $pop[[R]]{{$}}81declare <16 x i8> @llvm.ctpop.v16i8(<16 x i8>)82define <16 x i8> @popcnt_v16i8(<16 x i8> %x) {83 %a = call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %x)84 ret <16 x i8> %a85}86 87; CHECK-LABEL: any_v16i8:88; CHECK-NEXT: .functype any_v16i8 (v128) -> (i32){{$}}89; CHECK-NEXT: v128.any_true $push[[R:[0-9]+]]=, $0{{$}}90; CHECK-NEXT: return $pop[[R]]{{$}}91declare i32 @llvm.wasm.anytrue.v16i8(<16 x i8>)92define i32 @any_v16i8(<16 x i8> %x) {93 %a = call i32 @llvm.wasm.anytrue.v16i8(<16 x i8> %x)94 ret i32 %a95}96 97; CHECK-LABEL: all_v16i8:98; CHECK-NEXT: .functype all_v16i8 (v128) -> (i32){{$}}99; CHECK-NEXT: i8x16.all_true $push[[R:[0-9]+]]=, $0{{$}}100; CHECK-NEXT: return $pop[[R]]{{$}}101declare i32 @llvm.wasm.alltrue.v16i8(<16 x i8>)102define i32 @all_v16i8(<16 x i8> %x) {103 %a = call i32 @llvm.wasm.alltrue.v16i8(<16 x i8> %x)104 ret i32 %a105}106 107; CHECK-LABEL: bitmask_v16i8:108; CHECK-NEXT: .functype bitmask_v16i8 (v128) -> (i32){{$}}109; CHECK-NEXT: i8x16.bitmask $push[[R:[0-9]+]]=, $0{{$}}110; CHECK-NEXT: return $pop[[R]]{{$}}111declare i32 @llvm.wasm.bitmask.v16i8(<16 x i8>)112define i32 @bitmask_v16i8(<16 x i8> %x) {113 %a = call i32 @llvm.wasm.bitmask.v16i8(<16 x i8> %x)114 ret i32 %a115}116 117; CHECK-LABEL: bitselect_v16i8:118; CHECK-NEXT: .functype bitselect_v16i8 (v128, v128, v128) -> (v128){{$}}119; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}}120; CHECK-NEXT: return $pop[[R]]{{$}}121declare <16 x i8> @llvm.wasm.bitselect.v16i8(<16 x i8>, <16 x i8>, <16 x i8>)122define <16 x i8> @bitselect_v16i8(<16 x i8> %v1, <16 x i8> %v2, <16 x i8> %c) {123 %a = call <16 x i8> @llvm.wasm.bitselect.v16i8(124 <16 x i8> %v1, <16 x i8> %v2, <16 x i8> %c125 )126 ret <16 x i8> %a127}128 129; CHECK-LABEL: narrow_signed_v16i8:130; CHECK-NEXT: .functype narrow_signed_v16i8 (v128, v128) -> (v128){{$}}131; CHECK-NEXT: i8x16.narrow_i16x8_s $push[[R:[0-9]+]]=, $0, $1{{$}}132; CHECK-NEXT: return $pop[[R]]{{$}}133declare <16 x i8> @llvm.wasm.narrow.signed.v16i8.v8i16(<8 x i16>, <8 x i16>)134define <16 x i8> @narrow_signed_v16i8(<8 x i16> %low, <8 x i16> %high) {135 %a = call <16 x i8> @llvm.wasm.narrow.signed.v16i8.v8i16(136 <8 x i16> %low, <8 x i16> %high137 )138 ret <16 x i8> %a139}140 141; CHECK-LABEL: narrow_unsigned_v16i8:142; CHECK-NEXT: .functype narrow_unsigned_v16i8 (v128, v128) -> (v128){{$}}143; CHECK-NEXT: i8x16.narrow_i16x8_u $push[[R:[0-9]+]]=, $0, $1{{$}}144; CHECK-NEXT: return $pop[[R]]{{$}}145declare <16 x i8> @llvm.wasm.narrow.unsigned.v16i8.v8i16(<8 x i16>, <8 x i16>)146define <16 x i8> @narrow_unsigned_v16i8(<8 x i16> %low, <8 x i16> %high) {147 %a = call <16 x i8> @llvm.wasm.narrow.unsigned.v16i8.v8i16(148 <8 x i16> %low, <8 x i16> %high149 )150 ret <16 x i8> %a151}152 153; CHECK-LABEL: shuffle_v16i8:154; NO-CHECK-NOT: i8x16155; CHECK-NEXT: .functype shuffle_v16i8 (v128, v128) -> (v128){{$}}156; CHECK-NEXT: i8x16.shuffle $push[[R:[0-9]+]]=, $0, $1,157; CHECK-SAME: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0{{$}}158; CHECK-NEXT: return $pop[[R]]{{$}}159declare <16 x i8> @llvm.wasm.shuffle(160 <16 x i8>, <16 x i8>, i32 immarg, i32 immarg, i32 immarg, i32 immarg,161 i32 immarg, i32 immarg, i32 immarg, i32 immarg, i32 immarg, i32 immarg,162 i32 immarg, i32 immarg, i32 immarg, i32 immarg, i32 immarg, i32 immarg)163define <16 x i8> @shuffle_v16i8(<16 x i8> %x, <16 x i8> %y) {164 %res = call <16 x i8> @llvm.wasm.shuffle(<16 x i8> %x, <16 x i8> %y,165 i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7,166 i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 35)167 ret <16 x i8> %res168}169 170; CHECK-LABEL: laneselect_v16i8:171; CHECK-NEXT: .functype laneselect_v16i8 (v128, v128, v128) -> (v128){{$}}172; CHECK-NEXT: i8x16.relaxed_laneselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}}173; CHECK-NEXT: return $pop[[R]]{{$}}174declare <16 x i8> @llvm.wasm.relaxed.laneselect.v16i8(<16 x i8>, <16 x i8>, <16 x i8>)175define <16 x i8> @laneselect_v16i8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {176 %v = call <16 x i8> @llvm.wasm.relaxed.laneselect.v16i8(177 <16 x i8> %a, <16 x i8> %b, <16 x i8> %c178 )179 ret <16 x i8> %v180}181 182; CHECK-LABEL: relaxed_swizzle_v16i8:183; CHECK-NEXT: .functype relaxed_swizzle_v16i8 (v128, v128) -> (v128){{$}}184; CHECK-NEXT: i8x16.relaxed_swizzle $push[[R:[0-9]+]]=, $0, $1{{$}}185; CHECK-NEXT: return $pop[[R]]{{$}}186declare <16 x i8> @llvm.wasm.relaxed.swizzle(<16 x i8>, <16 x i8>)187define <16 x i8> @relaxed_swizzle_v16i8(<16 x i8> %x, <16 x i8> %y) {188 %a = call <16 x i8> @llvm.wasm.relaxed.swizzle(<16 x i8> %x, <16 x i8> %y)189 ret <16 x i8> %a190}191 192; ==============================================================================193; 8 x i16194; ==============================================================================195; CHECK-LABEL: add_sat_s_v8i16:196; CHECK-NEXT: .functype add_sat_s_v8i16 (v128, v128) -> (v128){{$}}197; CHECK-NEXT: i16x8.add_sat_s $push[[R:[0-9]+]]=, $0, $1{{$}}198; CHECK-NEXT: return $pop[[R]]{{$}}199declare <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16>, <8 x i16>)200define <8 x i16> @add_sat_s_v8i16(<8 x i16> %x, <8 x i16> %y) {201 %a = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> %x, <8 x i16> %y)202 ret <8 x i16> %a203}204 205; CHECK-LABEL: add_sat_u_v8i16:206; CHECK-NEXT: .functype add_sat_u_v8i16 (v128, v128) -> (v128){{$}}207; CHECK-NEXT: i16x8.add_sat_u $push[[R:[0-9]+]]=, $0, $1{{$}}208; CHECK-NEXT: return $pop[[R]]{{$}}209declare <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16>, <8 x i16>)210define <8 x i16> @add_sat_u_v8i16(<8 x i16> %x, <8 x i16> %y) {211 %a = call <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> %x, <8 x i16> %y)212 ret <8 x i16> %a213}214 215; CHECK-LABEL: sub_sat_s_v8i16:216; CHECK-NEXT: .functype sub_sat_s_v8i16 (v128, v128) -> (v128){{$}}217; CHECK-NEXT: i16x8.sub_sat_s $push[[R:[0-9]+]]=, $0, $1{{$}}218; CHECK-NEXT: return $pop[[R]]{{$}}219declare <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16>, <8 x i16>)220define <8 x i16> @sub_sat_s_v8i16(<8 x i16> %x, <8 x i16> %y) {221 %a = call <8 x i16> @llvm.ssub.sat.v8i16(222 <8 x i16> %x, <8 x i16> %y223 )224 ret <8 x i16> %a225}226 227; CHECK-LABEL: sub_sat_u_v8i16:228; CHECK-NEXT: .functype sub_sat_u_v8i16 (v128, v128) -> (v128){{$}}229; CHECK-NEXT: i16x8.sub_sat_u $push[[R:[0-9]+]]=, $0, $1{{$}}230; CHECK-NEXT: return $pop[[R]]{{$}}231declare <8 x i16> @llvm.usub.sat.v8i16(<8 x i16>, <8 x i16>)232define <8 x i16> @sub_sat_u_v8i16(<8 x i16> %x, <8 x i16> %y) {233 %a = call <8 x i16> @llvm.usub.sat.v8i16(234 <8 x i16> %x, <8 x i16> %y235 )236 ret <8 x i16> %a237}238 239; CHECK-LABEL: avgr_u_v8i16:240; CHECK-NEXT: .functype avgr_u_v8i16 (v128, v128) -> (v128){{$}}241; CHECK-NEXT: i16x8.avgr_u $push[[R:[0-9]+]]=, $0, $1{{$}}242; CHECK-NEXT: return $pop[[R]]{{$}}243declare <8 x i16> @llvm.wasm.avgr.unsigned.v8i16(<8 x i16>, <8 x i16>)244define <8 x i16> @avgr_u_v8i16(<8 x i16> %x, <8 x i16> %y) {245 %a = call <8 x i16> @llvm.wasm.avgr.unsigned.v8i16(<8 x i16> %x, <8 x i16> %y)246 ret <8 x i16> %a247}248 249; CHECK-LABEL: q15mulr_sat_s_v8i16:250; CHECK-NEXT: .functype q15mulr_sat_s_v8i16 (v128, v128) -> (v128){{$}}251; CHECK-NEXT: i16x8.q15mulr_sat_s $push[[R:[0-9]+]]=, $0, $1{{$}}252; CHECK-NEXT: return $pop[[R]]{{$}}253declare <8 x i16> @llvm.wasm.q15mulr.sat.signed(<8 x i16>, <8 x i16>)254define <8 x i16> @q15mulr_sat_s_v8i16(<8 x i16> %x, <8 x i16> %y) {255 %a = call <8 x i16> @llvm.wasm.q15mulr.sat.signed(<8 x i16> %x,256 <8 x i16> %y)257 ret <8 x i16> %a258}259 260; CHECK-LABEL: extadd_pairwise_s_v8i16:261; CHECK-NEXT: .functype extadd_pairwise_s_v8i16 (v128) -> (v128){{$}}262; CHECK-NEXT: i16x8.extadd_pairwise_i8x16_s $push[[R:[0-9]+]]=, $0{{$}}263; CHECK-NEXT: return $pop[[R]]{{$}}264declare <8 x i16> @llvm.wasm.extadd.pairwise.signed.v8i16(<16 x i8>)265define <8 x i16> @extadd_pairwise_s_v8i16(<16 x i8> %x) {266 %a = call <8 x i16> @llvm.wasm.extadd.pairwise.signed.v8i16(<16 x i8> %x)267 ret <8 x i16> %a268}269 270; CHECK-LABEL: extadd_pairwise_u_v8i16:271; CHECK-NEXT: .functype extadd_pairwise_u_v8i16 (v128) -> (v128){{$}}272; CHECK-NEXT: i16x8.extadd_pairwise_i8x16_u $push[[R:[0-9]+]]=, $0{{$}}273; CHECK-NEXT: return $pop[[R]]{{$}}274declare <8 x i16> @llvm.wasm.extadd.pairwise.unsigned.v8i16(<16 x i8>)275define <8 x i16> @extadd_pairwise_u_v8i16(<16 x i8> %x) {276 %a = call <8 x i16> @llvm.wasm.extadd.pairwise.unsigned.v8i16(<16 x i8> %x)277 ret <8 x i16> %a278}279 280; CHECK-LABEL: any_v8i16:281; CHECK-NEXT: .functype any_v8i16 (v128) -> (i32){{$}}282; CHECK-NEXT: v128.any_true $push[[R:[0-9]+]]=, $0{{$}}283; CHECK-NEXT: return $pop[[R]]{{$}}284declare i32 @llvm.wasm.anytrue.v8i16(<8 x i16>)285define i32 @any_v8i16(<8 x i16> %x) {286 %a = call i32 @llvm.wasm.anytrue.v8i16(<8 x i16> %x)287 ret i32 %a288}289 290; CHECK-LABEL: all_v8i16:291; CHECK-NEXT: .functype all_v8i16 (v128) -> (i32){{$}}292; CHECK-NEXT: i16x8.all_true $push[[R:[0-9]+]]=, $0{{$}}293; CHECK-NEXT: return $pop[[R]]{{$}}294declare i32 @llvm.wasm.alltrue.v8i16(<8 x i16>)295define i32 @all_v8i16(<8 x i16> %x) {296 %a = call i32 @llvm.wasm.alltrue.v8i16(<8 x i16> %x)297 ret i32 %a298}299 300; CHECK-LABEL: bitmask_v8i16:301; CHECK-NEXT: .functype bitmask_v8i16 (v128) -> (i32){{$}}302; CHECK-NEXT: i16x8.bitmask $push[[R:[0-9]+]]=, $0{{$}}303; CHECK-NEXT: return $pop[[R]]{{$}}304declare i32 @llvm.wasm.bitmask.v8i16(<8 x i16>)305define i32 @bitmask_v8i16(<8 x i16> %x) {306 %a = call i32 @llvm.wasm.bitmask.v8i16(<8 x i16> %x)307 ret i32 %a308}309 310; CHECK-LABEL: bitselect_v8i16:311; CHECK-NEXT: .functype bitselect_v8i16 (v128, v128, v128) -> (v128){{$}}312; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}}313; CHECK-NEXT: return $pop[[R]]{{$}}314declare <8 x i16> @llvm.wasm.bitselect.v8i16(<8 x i16>, <8 x i16>, <8 x i16>)315define <8 x i16> @bitselect_v8i16(<8 x i16> %v1, <8 x i16> %v2, <8 x i16> %c) {316 %a = call <8 x i16> @llvm.wasm.bitselect.v8i16(317 <8 x i16> %v1, <8 x i16> %v2, <8 x i16> %c318 )319 ret <8 x i16> %a320}321 322; CHECK-LABEL: narrow_signed_v8i16:323; CHECK-NEXT: .functype narrow_signed_v8i16 (v128, v128) -> (v128){{$}}324; CHECK-NEXT: i16x8.narrow_i32x4_s $push[[R:[0-9]+]]=, $0, $1{{$}}325; CHECK-NEXT: return $pop[[R]]{{$}}326declare <8 x i16> @llvm.wasm.narrow.signed.v8i16.v4i32(<4 x i32>, <4 x i32>)327define <8 x i16> @narrow_signed_v8i16(<4 x i32> %low, <4 x i32> %high) {328 %a = call <8 x i16> @llvm.wasm.narrow.signed.v8i16.v4i32(329 <4 x i32> %low, <4 x i32> %high330 )331 ret <8 x i16> %a332}333 334; CHECK-LABEL: narrow_unsigned_v8i16:335; CHECK-NEXT: .functype narrow_unsigned_v8i16 (v128, v128) -> (v128){{$}}336; CHECK-NEXT: i16x8.narrow_i32x4_u $push[[R:[0-9]+]]=, $0, $1{{$}}337; CHECK-NEXT: return $pop[[R]]{{$}}338declare <8 x i16> @llvm.wasm.narrow.unsigned.v8i16.v4i32(<4 x i32>, <4 x i32>)339define <8 x i16> @narrow_unsigned_v8i16(<4 x i32> %low, <4 x i32> %high) {340 %a = call <8 x i16> @llvm.wasm.narrow.unsigned.v8i16.v4i32(341 <4 x i32> %low, <4 x i32> %high342 )343 ret <8 x i16> %a344}345 346; CHECK-LABEL: laneselect_v8i16:347; CHECK-NEXT: .functype laneselect_v8i16 (v128, v128, v128) -> (v128){{$}}348; CHECK-NEXT: i16x8.relaxed_laneselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}}349; CHECK-NEXT: return $pop[[R]]{{$}}350declare <8 x i16> @llvm.wasm.relaxed.laneselect.v8i16(<8 x i16>, <8 x i16>, <8 x i16>)351define <8 x i16> @laneselect_v8i16(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) {352 %v = call <8 x i16> @llvm.wasm.relaxed.laneselect.v8i16(353 <8 x i16> %a, <8 x i16> %b, <8 x i16> %c354 )355 ret <8 x i16> %v356}357 358; CHECK-LABEL: relaxed_q15mulr_s_i16x8:359; CHECK-NEXT: .functype relaxed_q15mulr_s_i16x8 (v128, v128) -> (v128){{$}}360; CHECK-NEXT: i16x8.relaxed_q15mulr_s $push[[R:[0-9]+]]=, $0, $1{{$}}361; CHECK-NEXT: return $pop[[R]]{{$}}362declare <8 x i16> @llvm.wasm.relaxed.q15mulr.signed(<8 x i16>, <8 x i16>)363define <8 x i16> @relaxed_q15mulr_s_i16x8(<8 x i16> %a, <8 x i16> %b) {364 %v = call <8 x i16> @llvm.wasm.relaxed.q15mulr.signed(365 <8 x i16> %a, <8 x i16> %b366 )367 ret <8 x i16> %v368}369 370; CHECK-LABEL: dot_i8x16_i7x16_s_i16x8:371; CHECK-NEXT: .functype dot_i8x16_i7x16_s_i16x8 (v128, v128) -> (v128){{$}}372; CHECK-NEXT: i16x8.relaxed_dot_i8x16_i7x16_s $push[[R:[0-9]+]]=, $0, $1{{$}}373; CHECK-NEXT: return $pop[[R]]{{$}}374declare <8 x i16> @llvm.wasm.relaxed.dot.i8x16.i7x16.signed(<16 x i8>, <16 x i8>)375define <8 x i16> @dot_i8x16_i7x16_s_i16x8(<16 x i8> %a, <16 x i8> %b) {376 %v = call <8 x i16> @llvm.wasm.relaxed.dot.i8x16.i7x16.signed(377 <16 x i8> %a, <16 x i8> %b378 )379 ret <8 x i16> %v380}381 382; ==============================================================================383; 4 x i32384; ==============================================================================385; CHECK-LABEL: dot:386; CHECK-NEXT: .functype dot (v128, v128) -> (v128){{$}}387; CHECK-NEXT: i32x4.dot_i16x8_s $push[[R:[0-9]+]]=, $0, $1{{$}}388; CHECK-NEXT: return $pop[[R]]{{$}}389declare <4 x i32> @llvm.wasm.dot(<8 x i16>, <8 x i16>)390define <4 x i32> @dot(<8 x i16> %x, <8 x i16> %y) {391 %a = call <4 x i32> @llvm.wasm.dot(<8 x i16> %x, <8 x i16> %y)392 ret <4 x i32> %a393}394 395; CHECK-LABEL: extadd_pairwise_s_v4i32:396; CHECK-NEXT: .functype extadd_pairwise_s_v4i32 (v128) -> (v128){{$}}397; CHECK-NEXT: i32x4.extadd_pairwise_i16x8_s $push[[R:[0-9]+]]=, $0{{$}}398; CHECK-NEXT: return $pop[[R]]{{$}}399declare <4 x i32> @llvm.wasm.extadd.pairwise.signed.v4i32(<8 x i16>)400define <4 x i32> @extadd_pairwise_s_v4i32(<8 x i16> %x) {401 %a = call <4 x i32> @llvm.wasm.extadd.pairwise.signed.v4i32(<8 x i16> %x)402 ret <4 x i32> %a403}404 405; CHECK-LABEL: extadd_pairwise_u_v4i32:406; CHECK-NEXT: .functype extadd_pairwise_u_v4i32 (v128) -> (v128){{$}}407; CHECK-NEXT: i32x4.extadd_pairwise_i16x8_u $push[[R:[0-9]+]]=, $0{{$}}408; CHECK-NEXT: return $pop[[R]]{{$}}409declare <4 x i32> @llvm.wasm.extadd.pairwise.unsigned.v4i32(<8 x i16>)410define <4 x i32> @extadd_pairwise_u_v4i32(<8 x i16> %x) {411 %a = call <4 x i32> @llvm.wasm.extadd.pairwise.unsigned.v4i32(<8 x i16> %x)412 ret <4 x i32> %a413}414 415 416; CHECK-LABEL: any_v4i32:417; CHECK-NEXT: .functype any_v4i32 (v128) -> (i32){{$}}418; CHECK-NEXT: v128.any_true $push[[R:[0-9]+]]=, $0{{$}}419; CHECK-NEXT: return $pop[[R]]{{$}}420declare i32 @llvm.wasm.anytrue.v4i32(<4 x i32>)421define i32 @any_v4i32(<4 x i32> %x) {422 %a = call i32 @llvm.wasm.anytrue.v4i32(<4 x i32> %x)423 ret i32 %a424}425 426; CHECK-LABEL: all_v4i32:427; CHECK-NEXT: .functype all_v4i32 (v128) -> (i32){{$}}428; CHECK-NEXT: i32x4.all_true $push[[R:[0-9]+]]=, $0{{$}}429; CHECK-NEXT: return $pop[[R]]{{$}}430declare i32 @llvm.wasm.alltrue.v4i32(<4 x i32>)431define i32 @all_v4i32(<4 x i32> %x) {432 %a = call i32 @llvm.wasm.alltrue.v4i32(<4 x i32> %x)433 ret i32 %a434}435 436; CHECK-LABEL: bitmask_v4i32:437; CHECK-NEXT: .functype bitmask_v4i32 (v128) -> (i32){{$}}438; CHECK-NEXT: i32x4.bitmask $push[[R:[0-9]+]]=, $0{{$}}439; CHECK-NEXT: return $pop[[R]]{{$}}440declare i32 @llvm.wasm.bitmask.v4i32(<4 x i32>)441define i32 @bitmask_v4i32(<4 x i32> %x) {442 %a = call i32 @llvm.wasm.bitmask.v4i32(<4 x i32> %x)443 ret i32 %a444}445 446; CHECK-LABEL: bitselect_v4i32:447; CHECK-NEXT: .functype bitselect_v4i32 (v128, v128, v128) -> (v128){{$}}448; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}}449; CHECK-NEXT: return $pop[[R]]{{$}}450declare <4 x i32> @llvm.wasm.bitselect.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)451define <4 x i32> @bitselect_v4i32(<4 x i32> %v1, <4 x i32> %v2, <4 x i32> %c) {452 %a = call <4 x i32> @llvm.wasm.bitselect.v4i32(453 <4 x i32> %v1, <4 x i32> %v2, <4 x i32> %c454 )455 ret <4 x i32> %a456}457 458; CHECK-LABEL: trunc_sat_s_v4i32:459; NO-CHECK-NOT: f32x4460; CHECK-NEXT: .functype trunc_sat_s_v4i32 (v128) -> (v128){{$}}461; CHECK-NEXT: i32x4.trunc_sat_f32x4_s $push[[R:[0-9]+]]=, $0462; CHECK-NEXT: return $pop[[R]]463declare <4 x i32> @llvm.fptosi.sat.v4i32.v4f32(<4 x float>)464define <4 x i32> @trunc_sat_s_v4i32(<4 x float> %x) {465 %a = call <4 x i32> @llvm.fptosi.sat.v4i32.v4f32(<4 x float> %x)466 ret <4 x i32> %a467}468 469; CHECK-LABEL: trunc_sat_u_v4i32:470; NO-CHECK-NOT: f32x4471; CHECK-NEXT: .functype trunc_sat_u_v4i32 (v128) -> (v128){{$}}472; CHECK-NEXT: i32x4.trunc_sat_f32x4_u $push[[R:[0-9]+]]=, $0473; CHECK-NEXT: return $pop[[R]]474declare <4 x i32> @llvm.fptoui.sat.v4i32.v4f32(<4 x float>)475define <4 x i32> @trunc_sat_u_v4i32(<4 x float> %x) {476 %a = call <4 x i32> @llvm.fptoui.sat.v4i32.v4f32(<4 x float> %x)477 ret <4 x i32> %a478}479 480; CHECK-LABEL: trunc_sat_s_zero_v4i32:481; CHECK-NEXT: .functype trunc_sat_s_zero_v4i32 (v128) -> (v128){{$}}482; CHECK-NEXT: i32x4.trunc_sat_f64x2_s_zero $push[[R:[0-9]+]]=, $0{{$}}483; CHECK-NEXT: return $pop[[R]]{{$}}484declare <2 x i32> @llvm.fptosi.sat.v2i32.v2f64(<2 x double>)485define <4 x i32> @trunc_sat_s_zero_v4i32(<2 x double> %x) {486 %v = call <2 x i32> @llvm.fptosi.sat.v2i32.v2f64(<2 x double> %x)487 %a = shufflevector <2 x i32> %v, <2 x i32> <i32 0, i32 0>,488 <4 x i32> <i32 0, i32 1, i32 2, i32 3>489 ret <4 x i32> %a490}491 492; CHECK-LABEL: trunc_sat_s_zero_v4i32_2:493; CHECK-NEXT: .functype trunc_sat_s_zero_v4i32_2 (v128) -> (v128){{$}}494; SLOW-NEXT: i32x4.trunc_sat_f64x2_s_zero $push[[R:[0-9]+]]=, $0{{$}}495; SLOW-NEXT: return $pop[[R]]{{$}}496declare <4 x i32> @llvm.fptosi.sat.v4i32.v4f64(<4 x double>)497define <4 x i32> @trunc_sat_s_zero_v4i32_2(<2 x double> %x) {498 %v = shufflevector <2 x double> %x, <2 x double> zeroinitializer,499 <4 x i32> <i32 0, i32 1, i32 2, i32 3>500 %a = call <4 x i32> @llvm.fptosi.sat.v4i32.v4f64(<4 x double> %v)501 ret <4 x i32> %a502}503 504; CHECK-LABEL: trunc_sat_u_zero_v4i32:505; CHECK-NEXT: .functype trunc_sat_u_zero_v4i32 (v128) -> (v128){{$}}506; CHECK-NEXT: i32x4.trunc_sat_f64x2_u_zero $push[[R:[0-9]+]]=, $0{{$}}507; CHECK-NEXT: return $pop[[R]]{{$}}508declare <2 x i32> @llvm.fptoui.sat.v2i32.v2f64(<2 x double>)509define <4 x i32> @trunc_sat_u_zero_v4i32(<2 x double> %x) {510 %v = call <2 x i32> @llvm.fptoui.sat.v2i32.v2f64(<2 x double> %x)511 %a = shufflevector <2 x i32> %v, <2 x i32> <i32 0, i32 0>,512 <4 x i32> <i32 0, i32 1, i32 2, i32 3>513 ret <4 x i32> %a514}515 516; CHECK-LABEL: trunc_sat_u_zero_v4i32_2:517; CHECK-NEXT: .functype trunc_sat_u_zero_v4i32_2 (v128) -> (v128){{$}}518; SLOW-NEXT: i32x4.trunc_sat_f64x2_u_zero $push[[R:[0-9]+]]=, $0{{$}}519; SLOW-NEXT: return $pop[[R]]{{$}}520declare <4 x i32> @llvm.fptoui.sat.v4i32.v4f64(<4 x double>)521define <4 x i32> @trunc_sat_u_zero_v4i32_2(<2 x double> %x) {522 %v = shufflevector <2 x double> %x, <2 x double> zeroinitializer,523 <4 x i32> <i32 0, i32 1, i32 2, i32 3>524 %a = call <4 x i32> @llvm.fptoui.sat.v4i32.v4f64(<4 x double> %v)525 ret <4 x i32> %a526}527 528; CHECK-LABEL: laneselect_v4i32:529; CHECK-NEXT: .functype laneselect_v4i32 (v128, v128, v128) -> (v128){{$}}530; CHECK-NEXT: i32x4.relaxed_laneselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}}531; CHECK-NEXT: return $pop[[R]]{{$}}532declare <4 x i32> @llvm.wasm.relaxed.laneselect.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)533define <4 x i32> @laneselect_v4i32(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {534 %v = call <4 x i32> @llvm.wasm.relaxed.laneselect.v4i32(535 <4 x i32> %a, <4 x i32> %b, <4 x i32> %c536 )537 ret <4 x i32> %v538}539 540; CHECK-LABEL: relaxed_trunc_s:541; NO-CHECK-NOT: f32x4542; CHECK-NEXT: .functype relaxed_trunc_s (v128) -> (v128){{$}}543; CHECK-NEXT: i32x4.relaxed_trunc_f32x4_s $push[[R:[0-9]+]]=, $0544; CHECK-NEXT: return $pop[[R]]545declare <4 x i32> @llvm.wasm.relaxed.trunc.signed(<4 x float>)546define <4 x i32> @relaxed_trunc_s(<4 x float> %x) {547 %a = call <4 x i32> @llvm.wasm.relaxed.trunc.signed(<4 x float> %x)548 ret <4 x i32> %a549}550 551; CHECK-LABEL: relaxed_trunc_u:552; NO-CHECK-NOT: f32x4553; CHECK-NEXT: .functype relaxed_trunc_u (v128) -> (v128){{$}}554; CHECK-NEXT: i32x4.relaxed_trunc_f32x4_u $push[[R:[0-9]+]]=, $0555; CHECK-NEXT: return $pop[[R]]556declare <4 x i32> @llvm.wasm.relaxed.trunc.unsigned(<4 x float>)557define <4 x i32> @relaxed_trunc_u(<4 x float> %x) {558 %a = call <4 x i32> @llvm.wasm.relaxed.trunc.unsigned(<4 x float> %x)559 ret <4 x i32> %a560}561 562; CHECK-LABEL: relaxed_trunc_s_zero:563; CHECK-NEXT: .functype relaxed_trunc_s_zero (v128) -> (v128){{$}}564; CHECK-NEXT: i32x4.relaxed_trunc_f64x2_s_zero $push[[R:[0-9]+]]=, $0{{$}}565; CHECK-NEXT: return $pop[[R]]{{$}}566declare <4 x i32> @llvm.wasm.relaxed.trunc.signed.zero(<2 x double>)567define <4 x i32> @relaxed_trunc_s_zero(<2 x double> %x) {568 %a = call <4 x i32> @llvm.wasm.relaxed.trunc.signed.zero(<2 x double> %x)569 ret <4 x i32> %a570}571 572; CHECK-LABEL: relaxed_trunc_u_zero:573; CHECK-NEXT: .functype relaxed_trunc_u_zero (v128) -> (v128){{$}}574; CHECK-NEXT: i32x4.relaxed_trunc_f64x2_u_zero $push[[R:[0-9]+]]=, $0{{$}}575; CHECK-NEXT: return $pop[[R]]{{$}}576declare <4 x i32> @llvm.wasm.relaxed.trunc.unsigned.zero(<2 x double>)577define <4 x i32> @relaxed_trunc_u_zero(<2 x double> %x) {578 %a = call <4 x i32> @llvm.wasm.relaxed.trunc.unsigned.zero(<2 x double> %x)579 ret <4 x i32> %a580}581 582; CHECK-LABEL: dot_i8x16_i7x16_add_s_i32x4:583; CHECK-NEXT: .functype dot_i8x16_i7x16_add_s_i32x4 (v128, v128, v128) -> (v128){{$}}584; CHECK-NEXT: i32x4.relaxed_dot_i8x16_i7x16_add_s $push[[R:[0-9]+]]=, $0, $1, $2{{$}}585; CHECK-NEXT: return $pop[[R]]{{$}}586declare <4 x i32> @llvm.wasm.relaxed.dot.i8x16.i7x16.add.signed(587 <16 x i8>, <16 x i8>, <4 x i32>)588define <4 x i32> @dot_i8x16_i7x16_add_s_i32x4(<16 x i8> %a, <16 x i8> %b,589 <4 x i32> %c) {590 %v = call <4 x i32> @llvm.wasm.relaxed.dot.i8x16.i7x16.add.signed(591 <16 x i8> %a, <16 x i8> %b, <4 x i32> %c592 )593 ret <4 x i32> %v594}595 596; ==============================================================================597; 2 x i64598; ==============================================================================599; CHECK-LABEL: any_v2i64:600; CHECK-NEXT: .functype any_v2i64 (v128) -> (i32){{$}}601; CHECK-NEXT: v128.any_true $push[[R:[0-9]+]]=, $0{{$}}602; CHECK-NEXT: return $pop[[R]]{{$}}603declare i32 @llvm.wasm.anytrue.v2i64(<2 x i64>)604define i32 @any_v2i64(<2 x i64> %x) {605 %a = call i32 @llvm.wasm.anytrue.v2i64(<2 x i64> %x)606 ret i32 %a607}608 609; CHECK-LABEL: all_v2i64:610; CHECK-NEXT: .functype all_v2i64 (v128) -> (i32){{$}}611; CHECK-NEXT: i64x2.all_true $push[[R:[0-9]+]]=, $0{{$}}612; CHECK-NEXT: return $pop[[R]]{{$}}613declare i32 @llvm.wasm.alltrue.v2i64(<2 x i64>)614define i32 @all_v2i64(<2 x i64> %x) {615 %a = call i32 @llvm.wasm.alltrue.v2i64(<2 x i64> %x)616 ret i32 %a617}618 619; CHECK-LABEL: bitmask_v2i64:620; CHECK-NEXT: .functype bitmask_v2i64 (v128) -> (i32){{$}}621; CHECK-NEXT: i64x2.bitmask $push[[R:[0-9]+]]=, $0{{$}}622; CHECK-NEXT: return $pop[[R]]{{$}}623declare i32 @llvm.wasm.bitmask.v2i64(<2 x i64>)624define i32 @bitmask_v2i64(<2 x i64> %x) {625 %a = call i32 @llvm.wasm.bitmask.v2i64(<2 x i64> %x)626 ret i32 %a627}628 629; CHECK-LABEL: bitselect_v2i64:630; CHECK-NEXT: .functype bitselect_v2i64 (v128, v128, v128) -> (v128){{$}}631; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}}632; CHECK-NEXT: return $pop[[R]]{{$}}633declare <2 x i64> @llvm.wasm.bitselect.v2i64(<2 x i64>, <2 x i64>, <2 x i64>)634define <2 x i64> @bitselect_v2i64(<2 x i64> %v1, <2 x i64> %v2, <2 x i64> %c) {635 %a = call <2 x i64> @llvm.wasm.bitselect.v2i64(636 <2 x i64> %v1, <2 x i64> %v2, <2 x i64> %c637 )638 ret <2 x i64> %a639}640 641; CHECK-LABEL: laneselect_v2i64:642; CHECK-NEXT: .functype laneselect_v2i64 (v128, v128, v128) -> (v128){{$}}643; CHECK-NEXT: i64x2.relaxed_laneselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}}644; CHECK-NEXT: return $pop[[R]]{{$}}645declare <2 x i64> @llvm.wasm.relaxed.laneselect.v2i64(<2 x i64>, <2 x i64>, <2 x i64>)646define <2 x i64> @laneselect_v2i64(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) {647 %v = call <2 x i64> @llvm.wasm.relaxed.laneselect.v2i64(648 <2 x i64> %a, <2 x i64> %b, <2 x i64> %c649 )650 ret <2 x i64> %v651}652 653; ==============================================================================654; 4 x f32655; ==============================================================================656; CHECK-LABEL: bitselect_v4f32:657; CHECK-NEXT: .functype bitselect_v4f32 (v128, v128, v128) -> (v128){{$}}658; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}}659; CHECK-NEXT: return $pop[[R]]{{$}}660declare <4 x float> @llvm.wasm.bitselect.v4f32(<4 x float>, <4 x float>, <4 x float>)661define <4 x float> @bitselect_v4f32(<4 x float> %v1, <4 x float> %v2, <4 x float> %c) {662 %a = call <4 x float> @llvm.wasm.bitselect.v4f32(663 <4 x float> %v1, <4 x float> %v2, <4 x float> %c664 )665 ret <4 x float> %a666}667 668; CHECK-LABEL: pmin_v4f32:669; CHECK-NEXT: .functype pmin_v4f32 (v128, v128) -> (v128){{$}}670; CHECK-NEXT: f32x4.pmin $push[[R:[0-9]+]]=, $0, $1{{$}}671; CHECK-NEXT: return $pop[[R]]{{$}}672declare <4 x float> @llvm.wasm.pmin.v4f32(<4 x float>, <4 x float>)673define <4 x float> @pmin_v4f32(<4 x float> %a, <4 x float> %b) {674 %v = call <4 x float> @llvm.wasm.pmin.v4f32(<4 x float> %a, <4 x float> %b)675 ret <4 x float> %v676}677 678; CHECK-LABEL: pmax_v4f32:679; CHECK-NEXT: .functype pmax_v4f32 (v128, v128) -> (v128){{$}}680; CHECK-NEXT: f32x4.pmax $push[[R:[0-9]+]]=, $0, $1{{$}}681; CHECK-NEXT: return $pop[[R]]{{$}}682declare <4 x float> @llvm.wasm.pmax.v4f32(<4 x float>, <4 x float>)683define <4 x float> @pmax_v4f32(<4 x float> %a, <4 x float> %b) {684 %v = call <4 x float> @llvm.wasm.pmax.v4f32(<4 x float> %a, <4 x float> %b)685 ret <4 x float> %v686}687 688; CHECK-LABEL: ceil_v4f32:689; CHECK-NEXT: .functype ceil_v4f32 (v128) -> (v128){{$}}690; CHECK-NEXT: f32x4.ceil $push[[R:[0-9]+]]=, $0{{$}}691; CHECK-NEXT: return $pop[[R]]{{$}}692declare <4 x float> @llvm.ceil.v4f32(<4 x float>)693define <4 x float> @ceil_v4f32(<4 x float> %a) {694 %v = call <4 x float> @llvm.ceil.v4f32(<4 x float> %a)695 ret <4 x float> %v696}697 698; CHECK-LABEL: floor_v4f32:699; CHECK-NEXT: .functype floor_v4f32 (v128) -> (v128){{$}}700; CHECK-NEXT: f32x4.floor $push[[R:[0-9]+]]=, $0{{$}}701; CHECK-NEXT: return $pop[[R]]{{$}}702declare <4 x float> @llvm.floor.v4f32(<4 x float>)703define <4 x float> @floor_v4f32(<4 x float> %a) {704 %v = call <4 x float> @llvm.floor.v4f32(<4 x float> %a)705 ret <4 x float> %v706}707 708; CHECK-LABEL: trunc_v4f32:709; CHECK-NEXT: .functype trunc_v4f32 (v128) -> (v128){{$}}710; CHECK-NEXT: f32x4.trunc $push[[R:[0-9]+]]=, $0{{$}}711; CHECK-NEXT: return $pop[[R]]{{$}}712declare <4 x float> @llvm.trunc.v4f32(<4 x float>)713define <4 x float> @trunc_v4f32(<4 x float> %a) {714 %v = call <4 x float> @llvm.trunc.v4f32(<4 x float> %a)715 ret <4 x float> %v716}717 718; CHECK-LABEL: nearest_v4f32:719; CHECK-NEXT: .functype nearest_v4f32 (v128) -> (v128){{$}}720; CHECK-NEXT: f32x4.nearest $push[[R:[0-9]+]]=, $0{{$}}721; CHECK-NEXT: return $pop[[R]]{{$}}722declare <4 x float> @llvm.nearbyint.v4f32(<4 x float>)723define <4 x float> @nearest_v4f32(<4 x float> %a) {724 %v = call <4 x float> @llvm.nearbyint.v4f32(<4 x float> %a)725 ret <4 x float> %v726}727 728; CHECK-LABEL: nearest_v4f32_via_rint:729; CHECK-NEXT: .functype nearest_v4f32_via_rint (v128) -> (v128){{$}}730; CHECK-NEXT: f32x4.nearest $push[[R:[0-9]+]]=, $0{{$}}731; CHECK-NEXT: return $pop[[R]]{{$}}732declare <4 x float> @llvm.rint.v4f32(<4 x float>)733define <4 x float> @nearest_v4f32_via_rint(<4 x float> %a) {734 %v = call <4 x float> @llvm.rint.v4f32(<4 x float> %a)735 ret <4 x float> %v736}737 738; CHECK-LABEL: nearest_v4f32_via_roundeven:739; CHECK-NEXT: .functype nearest_v4f32_via_roundeven (v128) -> (v128){{$}}740; CHECK-NEXT: f32x4.nearest $push[[R:[0-9]+]]=, $0{{$}}741; CHECK-NEXT: return $pop[[R]]{{$}}742declare <4 x float> @llvm.roundeven.v4f32(<4 x float>)743define <4 x float> @nearest_v4f32_via_roundeven(<4 x float> %a) {744 %v = call <4 x float> @llvm.roundeven.v4f32(<4 x float> %a)745 ret <4 x float> %v746}747 748; CHECK-LABEL: madd_v4f32:749; CHECK-NEXT: .functype madd_v4f32 (v128, v128, v128) -> (v128){{$}}750; CHECK-NEXT: f32x4.relaxed_madd $push[[R:[0-9]+]]=, $0, $1, $2{{$}}751; CHECK-NEXT: return $pop[[R]]{{$}}752declare <4 x float> @llvm.wasm.relaxed.madd.v4f32(<4 x float>, <4 x float>, <4 x float>)753define <4 x float> @madd_v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %c) {754 %v = call <4 x float> @llvm.wasm.relaxed.madd.v4f32(755 <4 x float> %a, <4 x float> %b, <4 x float> %c756 )757 ret <4 x float> %v758}759 760; CHECK-LABEL: nmadd_v4f32:761; CHECK-NEXT: .functype nmadd_v4f32 (v128, v128, v128) -> (v128){{$}}762; CHECK-NEXT: f32x4.relaxed_nmadd $push[[R:[0-9]+]]=, $0, $1, $2{{$}}763; CHECK-NEXT: return $pop[[R]]{{$}}764declare <4 x float> @llvm.wasm.relaxed.nmadd.v4f32(<4 x float>, <4 x float>, <4 x float>)765define <4 x float> @nmadd_v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %c) {766 %v = call <4 x float> @llvm.wasm.relaxed.nmadd.v4f32(767 <4 x float> %a, <4 x float> %b, <4 x float> %c768 )769 ret <4 x float> %v770}771 772; CHECK-LABEL: relaxed_min_v4f32:773; CHECK-NEXT: .functype relaxed_min_v4f32 (v128, v128) -> (v128){{$}}774; CHECK-NEXT: f32x4.relaxed_min $push[[R:[0-9]+]]=, $0, $1{{$}}775; CHECK-NEXT: return $pop[[R]]{{$}}776declare <4 x float> @llvm.wasm.relaxed.min.v4f32(<4 x float>, <4 x float>)777define <4 x float> @relaxed_min_v4f32(<4 x float> %a, <4 x float> %b) {778 %v = call <4 x float> @llvm.wasm.relaxed.min.v4f32(779 <4 x float> %a, <4 x float> %b780 )781 ret <4 x float> %v782}783 784; CHECK-LABEL: relaxed_max_v4f32:785; CHECK-NEXT: .functype relaxed_max_v4f32 (v128, v128) -> (v128){{$}}786; CHECK-NEXT: f32x4.relaxed_max $push[[R:[0-9]+]]=, $0, $1{{$}}787; CHECK-NEXT: return $pop[[R]]{{$}}788declare <4 x float> @llvm.wasm.relaxed.max.v4f32(<4 x float>, <4 x float>)789define <4 x float> @relaxed_max_v4f32(<4 x float> %a, <4 x float> %b) {790 %v = call <4 x float> @llvm.wasm.relaxed.max.v4f32(791 <4 x float> %a, <4 x float> %b792 )793 ret <4 x float> %v794}795 796; CHECK-LABEL: relaxed_dot_bf16x8_add_f32:797; CHECK-NEXT: .functype relaxed_dot_bf16x8_add_f32 (v128, v128, v128) -> (v128){{$}}798; CHECK-NEXT: f32x4.relaxed_dot_bf16x8_add_f32 $push[[R:[0-9]+]]=, $0, $1, $2{{$}}799; CHECK-NEXT: return $pop[[R]]{{$}}800declare <4 x float> @llvm.wasm.relaxed.dot.bf16x8.add.f32(<8 x i16>, <8 x i16>,801 <4 x float>)802define <4 x float> @relaxed_dot_bf16x8_add_f32(<8 x i16> %a, <8 x i16> %b,803 <4 x float> %c) {804 %v = call <4 x float> @llvm.wasm.relaxed.dot.bf16x8.add.f32(805 <8 x i16> %a, <8 x i16> %b, <4 x float> %c806 )807 ret <4 x float> %v808}809 810; ==============================================================================811; 2 x f64812; ==============================================================================813; CHECK-LABEL: bitselect_v2f64:814; CHECK-NEXT: .functype bitselect_v2f64 (v128, v128, v128) -> (v128){{$}}815; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}}816; CHECK-NEXT: return $pop[[R]]{{$}}817declare <2 x double> @llvm.wasm.bitselect.v2f64(<2 x double>, <2 x double>, <2 x double>)818define <2 x double> @bitselect_v2f64(<2 x double> %v1, <2 x double> %v2, <2 x double> %c) {819 %a = call <2 x double> @llvm.wasm.bitselect.v2f64(820 <2 x double> %v1, <2 x double> %v2, <2 x double> %c821 )822 ret <2 x double> %a823}824 825; CHECK-LABEL: pmin_v2f64:826; CHECK-NEXT: .functype pmin_v2f64 (v128, v128) -> (v128){{$}}827; CHECK-NEXT: f64x2.pmin $push[[R:[0-9]+]]=, $0, $1{{$}}828; CHECK-NEXT: return $pop[[R]]{{$}}829declare <2 x double> @llvm.wasm.pmin.v2f64(<2 x double>, <2 x double>)830define <2 x double> @pmin_v2f64(<2 x double> %a, <2 x double> %b) {831 %v = call <2 x double> @llvm.wasm.pmin.v2f64(<2 x double> %a, <2 x double> %b)832 ret <2 x double> %v833}834 835; CHECK-LABEL: pmax_v2f64:836; CHECK-NEXT: .functype pmax_v2f64 (v128, v128) -> (v128){{$}}837; CHECK-NEXT: f64x2.pmax $push[[R:[0-9]+]]=, $0, $1{{$}}838; CHECK-NEXT: return $pop[[R]]{{$}}839declare <2 x double> @llvm.wasm.pmax.v2f64(<2 x double>, <2 x double>)840define <2 x double> @pmax_v2f64(<2 x double> %a, <2 x double> %b) {841 %v = call <2 x double> @llvm.wasm.pmax.v2f64(<2 x double> %a, <2 x double> %b)842 ret <2 x double> %v843}844 845; CHECK-LABEL: ceil_v2f64:846; CHECK-NEXT: .functype ceil_v2f64 (v128) -> (v128){{$}}847; CHECK-NEXT: f64x2.ceil $push[[R:[0-9]+]]=, $0{{$}}848; CHECK-NEXT: return $pop[[R]]{{$}}849declare <2 x double> @llvm.ceil.v2f64(<2 x double>)850define <2 x double> @ceil_v2f64(<2 x double> %a) {851 %v = call <2 x double> @llvm.ceil.v2f64(<2 x double> %a)852 ret <2 x double> %v853}854 855; CHECK-LABEL: floor_v2f64:856; CHECK-NEXT: .functype floor_v2f64 (v128) -> (v128){{$}}857; CHECK-NEXT: f64x2.floor $push[[R:[0-9]+]]=, $0{{$}}858; CHECK-NEXT: return $pop[[R]]{{$}}859declare <2 x double> @llvm.floor.v2f64(<2 x double>)860define <2 x double> @floor_v2f64(<2 x double> %a) {861 %v = call <2 x double> @llvm.floor.v2f64(<2 x double> %a)862 ret <2 x double> %v863}864 865; CHECK-LABEL: trunc_v2f64:866; CHECK-NEXT: .functype trunc_v2f64 (v128) -> (v128){{$}}867; CHECK-NEXT: f64x2.trunc $push[[R:[0-9]+]]=, $0{{$}}868; CHECK-NEXT: return $pop[[R]]{{$}}869declare <2 x double> @llvm.trunc.v2f64(<2 x double>)870define <2 x double> @trunc_v2f64(<2 x double> %a) {871 %v = call <2 x double> @llvm.trunc.v2f64(<2 x double> %a)872 ret <2 x double> %v873}874 875; CHECK-LABEL: nearest_v2f64:876; CHECK-NEXT: .functype nearest_v2f64 (v128) -> (v128){{$}}877; CHECK-NEXT: f64x2.nearest $push[[R:[0-9]+]]=, $0{{$}}878; CHECK-NEXT: return $pop[[R]]{{$}}879declare <2 x double> @llvm.nearbyint.v2f64(<2 x double>)880define <2 x double> @nearest_v2f64(<2 x double> %a) {881 %v = call <2 x double> @llvm.nearbyint.v2f64(<2 x double> %a)882 ret <2 x double> %v883}884 885; CHECK-LABEL: nearest_v2f64_via_rint:886; CHECK-NEXT: .functype nearest_v2f64_via_rint (v128) -> (v128){{$}}887; CHECK-NEXT: f64x2.nearest $push[[R:[0-9]+]]=, $0{{$}}888; CHECK-NEXT: return $pop[[R]]{{$}}889declare <2 x double> @llvm.rint.v2f64(<2 x double>)890define <2 x double> @nearest_v2f64_via_rint(<2 x double> %a) {891 %v = call <2 x double> @llvm.rint.v2f64(<2 x double> %a)892 ret <2 x double> %v893}894 895; CHECK-LABEL: nearest_v2f64_via_roundeven:896; CHECK-NEXT: .functype nearest_v2f64_via_roundeven (v128) -> (v128){{$}}897; CHECK-NEXT: f64x2.nearest $push[[R:[0-9]+]]=, $0{{$}}898; CHECK-NEXT: return $pop[[R]]{{$}}899declare <2 x double> @llvm.roundeven.v2f64(<2 x double>)900define <2 x double> @nearest_v2f64_via_roundeven(<2 x double> %a) {901 %v = call <2 x double> @llvm.roundeven.v2f64(<2 x double> %a)902 ret <2 x double> %v903}904 905; CHECK-LABEL: madd_v2f64:906; CHECK-NEXT: .functype madd_v2f64 (v128, v128, v128) -> (v128){{$}}907; CHECK-NEXT: f64x2.relaxed_madd $push[[R:[0-9]+]]=, $0, $1, $2{{$}}908; CHECK-NEXT: return $pop[[R]]{{$}}909declare <2 x double> @llvm.wasm.relaxed.madd.v2f64(910 <2 x double>, <2 x double>, <2 x double>)911define <2 x double> @madd_v2f64(<2 x double> %a, <2 x double> %b, <2 x double> %c) {912 %v = call <2 x double> @llvm.wasm.relaxed.madd.v2f64(913 <2 x double> %a, <2 x double> %b, <2 x double> %c914 )915 ret <2 x double> %v916}917 918; CHECK-LABEL: nmadd_v2f64:919; CHECK-NEXT: .functype nmadd_v2f64 (v128, v128, v128) -> (v128){{$}}920; CHECK-NEXT: f64x2.relaxed_nmadd $push[[R:[0-9]+]]=, $0, $1, $2{{$}}921; CHECK-NEXT: return $pop[[R]]{{$}}922declare <2 x double> @llvm.wasm.relaxed.nmadd.v2f64(923 <2 x double>, <2 x double>, <2 x double>)924define <2 x double> @nmadd_v2f64(<2 x double> %a, <2 x double> %b, <2 x double> %c) {925 %v = call <2 x double> @llvm.wasm.relaxed.nmadd.v2f64(926 <2 x double> %a, <2 x double> %b, <2 x double> %c927 )928 ret <2 x double> %v929}930 931; CHECK-LABEL: relaxed_min_v2f64:932; CHECK-NEXT: .functype relaxed_min_v2f64 (v128, v128) -> (v128){{$}}933; CHECK-NEXT: f64x2.relaxed_min $push[[R:[0-9]+]]=, $0, $1{{$}}934; CHECK-NEXT: return $pop[[R]]{{$}}935declare <2 x double> @llvm.wasm.relaxed.min.v2f64(<2 x double>, <2 x double>)936define <2 x double> @relaxed_min_v2f64(<2 x double> %a, <2 x double> %b) {937 %v = call <2 x double> @llvm.wasm.relaxed.min.v2f64(938 <2 x double> %a, <2 x double> %b939 )940 ret <2 x double> %v941}942 943; CHECK-LABEL: relaxed_max_v2f64:944; CHECK-NEXT: .functype relaxed_max_v2f64 (v128, v128) -> (v128){{$}}945; CHECK-NEXT: f64x2.relaxed_max $push[[R:[0-9]+]]=, $0, $1{{$}}946; CHECK-NEXT: return $pop[[R]]{{$}}947declare <2 x double> @llvm.wasm.relaxed.max.v2f64(<2 x double>, <2 x double>)948define <2 x double> @relaxed_max_v2f64(<2 x double> %a, <2 x double> %b) {949 %v = call <2 x double> @llvm.wasm.relaxed.max.v2f64(950 <2 x double> %a, <2 x double> %b951 )952 ret <2 x double> %v953}954