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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -verify-machineinstrs -mattr=+simd128 | FileCheck %s3 4; Regression test for an issue in which DAG combines created a constant i8x165; vector with lane values of 255, which was outside the -128 to 127 range6; expected by our ISel patterns (and similar for the i16 version) and caused an7; ISel failure. The fix was to adjust out-of-range values manually in8; BUILD_VECTOR lowering.9 10target triple = "wasm32-unknown-unknown"11 12define <4 x i8> @test_i8(<4 x i8> %b) {13; CHECK-LABEL: test_i8:14; CHECK: .functype test_i8 (v128) -> (v128)15; CHECK-NEXT: # %bb.0:16; CHECK-NEXT: v128.const 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 117; CHECK-NEXT: local.get 018; CHECK-NEXT: v128.andnot19; CHECK-NEXT: # fallthrough-return20 %c = and <4 x i8> %b, <i8 1, i8 1, i8 1, i8 1>21 %d = xor <4 x i8> %c, <i8 1, i8 1, i8 1, i8 1>22 ret <4 x i8> %d23}24 25define <4 x i16> @test_i16(<4 x i16> %b) {26; CHECK-LABEL: test_i16:27; CHECK: .functype test_i16 (v128) -> (v128)28; CHECK-NEXT: # %bb.0:29; CHECK-NEXT: v128.const 1, 1, 1, 1, 1, 1, 1, 130; CHECK-NEXT: local.get 031; CHECK-NEXT: v128.andnot32; CHECK-NEXT: # fallthrough-return33 %c = and <4 x i16> %b, <i16 1, i16 1, i16 1, i16 1>34 %d = xor <4 x i16> %c, <i16 1, i16 1, i16 1, i16 1>35 ret <4 x i16> %d36}37