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1; RUN: llc < %s -mattr=+simd128 -verify-machineinstrs2 3target triple = "wasm32-unknown-unknown"4 5; After DAG legalization, in SelectionDAG optimization phase, ISel runs6; DAGCombiner on each node, among which SimplifyDemandedVectorElts turns unused7; vector elements into undefs. And in order to make sure the DAG is in a8; legalized state, it runs legalization again, which runs our custom9; LowerBUILD_VECTOR, which converts undefs into zeros, causing an infinite loop.10; We prevent this from happening by creating a custom hook , which allows us to11; bail out of SimplifyDemandedVectorElts after legalization.12 13; This is a reduced test case from a bug reproducer reported. This should not14; hang.15define void @test(i8 %0) {16 %2 = insertelement <4 x i8> <i8 -1, i8 -1, i8 -1, i8 poison>, i8 %0, i64 317 %3 = zext <4 x i8> %2 to <4 x i32>18 %4 = mul nuw nsw <4 x i32> %3, <i32 257, i32 257, i32 257, i32 257>19 %5 = add nuw nsw <4 x i32> %4, <i32 1, i32 1, i32 1, i32 1>20 %6 = lshr <4 x i32> %5, <i32 1, i32 1, i32 1, i32 1>21 %7 = mul nuw nsw <4 x i32> %6, <i32 20000, i32 20000, i32 20000, i32 20000>22 %8 = add nuw nsw <4 x i32> %7, <i32 32768, i32 32768, i32 32768, i32 32768>23 %9 = and <4 x i32> %8, <i32 2147418112, i32 2147418112, i32 2147418112, i32 2147418112>24 %10 = sub nsw <4 x i32> <i32 655360000, i32 655360000, i32 655360000, i32 655360000>, %925 %11 = ashr exact <4 x i32> %10, <i32 16, i32 16, i32 16, i32 16>26 %12 = trunc <4 x i32> %11 to <4 x i16>27 store <4 x i16> %12, ptr undef, align 428 ret void29}30