52 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=i386-apple-darwin | FileCheck %s3; The inner loop should use [reg] addressing, not [reg+reg] addressing.4; rdar://64039655 6target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"7target triple = "i386-apple-darwin9.5"8 9define ptr @test(ptr %Q, ptr %L) nounwind {10; CHECK-LABEL: test:11; CHECK: ## %bb.0: ## %entry12; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax13; CHECK-NEXT: jmp LBB0_214; CHECK-NEXT: .p2align 415; CHECK-NEXT: LBB0_1: ## %bb16; CHECK-NEXT: ## in Loop: Header=BB0_2 Depth=117; CHECK-NEXT: incl %eax18; CHECK-NEXT: LBB0_2: ## %bb119; CHECK-NEXT: ## =>This Inner Loop Header: Depth=120; CHECK-NEXT: movzbl (%eax), %ecx21; CHECK-NEXT: cmpl $12, %ecx22; CHECK-NEXT: je LBB0_123; CHECK-NEXT: ## %bb.3: ## %bb124; CHECK-NEXT: ## in Loop: Header=BB0_2 Depth=125; CHECK-NEXT: cmpl $42, %ecx26; CHECK-NEXT: je LBB0_127; CHECK-NEXT: ## %bb.4: ## %bb328; CHECK-NEXT: movb $4, 2(%eax)29; CHECK-NEXT: retl30entry:31 br label %bb132 33bb: ; preds = %bb1, %bb134 %indvar.next = add i32 %P.0.rec, 1 ; <i32> [#uses=1]35 br label %bb136 37bb1: ; preds = %bb, %entry38 %P.0.rec = phi i32 [ 0, %entry ], [ %indvar.next, %bb ] ; <i32> [#uses=3]39 %P.0 = getelementptr i8, ptr %Q, i32 %P.0.rec ; <ptr> [#uses=2]40 %0 = load i8, ptr %P.0, align 1 ; <i8> [#uses=1]41 switch i8 %0, label %bb3 [42 i8 12, label %bb43 i8 42, label %bb44 ]45 46bb3: ; preds = %bb147 %P.0.sum = add i32 %P.0.rec, 2 ; <i32> [#uses=1]48 %1 = getelementptr i8, ptr %Q, i32 %P.0.sum ; <ptr> [#uses=1]49 store i8 4, ptr %1, align 150 ret ptr %P.051}52