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1; RUN: llc < %s2; PR63723;4; This test produces a move instruction with an implicitly defined super-register:5;6; %DL = MOV8rr killed %reg1038, implicit-def %RDX7;8; When %DL is rematerialized, we must remember to update live intervals for9; sub-registers %DX and %EDX.10 11target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"12target triple = "x86_64-apple-darwin10.0.0"13 14define noalias ptr @foo() nounwind ssp {15entry:16 br i1 undef, label %for.end, label %for.body17 18for.body: ; preds = %if.end40, %entry19 %tmp6 = load i8, ptr undef, align 2 ; <i8> [#uses=3]20 %conv11 = sext i8 %tmp6 to i64 ; <i64> [#uses=1]21 %cmp15 = icmp slt i64 %conv11, undef ; <i1> [#uses=1]22 br i1 %cmp15, label %if.end, label %if.then23 24if.then: ; preds = %for.body25 %conv18 = sext i8 %tmp6 to i32 ; <i32> [#uses=1]26 %call = tail call i32 (...) @invalid(i32 0, i32 0, i32 %conv18) nounwind ; <i32> [#uses=0]27 br label %if.end28 29if.end: ; preds = %if.then, %for.body30 %index.0 = phi i8 [ 0, %if.then ], [ %tmp6, %for.body ] ; <i8> [#uses=1]31 store i8 %index.0, ptr undef32 %tmp24 = load i8, ptr undef ; <i8> [#uses=2]33 br i1 undef, label %if.end40, label %if.then3634 35if.then36: ; preds = %if.end36 %conv38 = sext i8 %tmp24 to i32 ; <i32> [#uses=1]37 %call39 = tail call i32 (...) @invalid(i32 0, i32 0, i32 %conv38) nounwind ; <i32> [#uses=0]38 br label %if.end4039 40if.end40: ; preds = %if.then36, %if.end41 %index.1 = phi i8 [ 0, %if.then36 ], [ %tmp24, %if.end ] ; <i8> [#uses=1]42 store i8 %index.1, ptr undef43 br i1 false, label %for.body, label %for.end44 45for.end: ; preds = %if.end40, %entry46 ret ptr undef47}48 49declare i32 @invalid(...)50