100 lines · plain
1; RUN: llc < %s -mcpu=corei7-avx -mattr=+avx | FileCheck %s2target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"3target triple = "x86_64-apple-darwin11"4 5; This test would create a vpand %ymm instruction that is only legal in AVX2.6; CHECK-NOT: vpand %ymm7 8declare i32 @llvm.x86.avx.movmsk.ps.256(<8 x float>) nounwind readnone9 10define void @ShadeTile() nounwind {11allocas:12 br i1 undef, label %if_then, label %if_else13 14if_then: ; preds = %allocas15 unreachable16 17if_else: ; preds = %allocas18 br i1 undef, label %for_loop156.lr.ph, label %if_exit19 20for_loop156.lr.ph: ; preds = %if_else21 %val_6.i21244 = load i16, ptr undef, align 222 %0 = insertelement <8 x i16> undef, i16 %val_6.i21244, i32 623 %val_7.i21248 = load i16, ptr undef, align 224 %1 = insertelement <8 x i16> %0, i16 %val_7.i21248, i32 725 %uint2uint32.i20206 = zext <8 x i16> %1 to <8 x i32>26 %bitop5.i20208 = and <8 x i32> %uint2uint32.i20206, <i32 31744, i32 31744, i32 31744, i32 31744, i32 31744, i32 31744, i32 31744, i32 31744>27 %bitop8.i20209 = and <8 x i32> %uint2uint32.i20206, <i32 1023, i32 1023, i32 1023, i32 1023, i32 1023, i32 1023, i32 1023, i32 1023>28 %bitop12.i20211 = lshr <8 x i32> %bitop5.i20208, <i32 10, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10>29 %binop13.i20212 = add <8 x i32> %bitop12.i20211, <i32 112, i32 112, i32 112, i32 112, i32 112, i32 112, i32 112, i32 112>30 %bitop15.i20213 = shl <8 x i32> %binop13.i20212, <i32 23, i32 23, i32 23, i32 23, i32 23, i32 23, i32 23, i32 23>31 %bitop17.i20214 = shl <8 x i32> %bitop8.i20209, <i32 13, i32 13, i32 13, i32 13, i32 13, i32 13, i32 13, i32 13>32 %bitop20.i20215 = or <8 x i32> undef, %bitop15.i2021333 %bitop22.i20216 = or <8 x i32> %bitop20.i20215, %bitop17.i2021434 %int_to_float_bitcast.i.i.i20217 = bitcast <8 x i32> %bitop22.i20216 to <8 x float>35 %binop401 = fmul <8 x float> undef, <float 4.000000e+00, float 4.000000e+00, float 4.000000e+00, float 4.000000e+00, float 4.000000e+00, float 4.000000e+00, float 4.000000e+00, float 4.000000e+00>36 %binop402 = fadd <8 x float> %binop401, <float -2.000000e+00, float -2.000000e+00, float -2.000000e+00, float -2.000000e+00, float -2.000000e+00, float -2.000000e+00, float -2.000000e+00, float -2.000000e+00>37 %binop403 = fmul <8 x float> zeroinitializer, %binop40238 %binop406 = fmul <8 x float> %int_to_float_bitcast.i.i.i20217, <float 4.000000e+00, float 4.000000e+00, float 4.000000e+00, float 4.000000e+00, float 4.000000e+00, float 4.000000e+00, float 4.000000e+00, float 4.000000e+00>39 %binop407 = fadd <8 x float> %binop406, <float -2.000000e+00, float -2.000000e+00, float -2.000000e+00, float -2.000000e+00, float -2.000000e+00, float -2.000000e+00, float -2.000000e+00, float -2.000000e+00>40 %binop408 = fmul <8 x float> zeroinitializer, %binop40741 %binop411 = fsub <8 x float> <float 3.000000e+00, float 3.000000e+00, float 3.000000e+00, float 3.000000e+00, float 3.000000e+00, float 3.000000e+00, float 3.000000e+00, float 3.000000e+00>, undef42 %val_4.i21290 = load i16, ptr undef, align 243 %2 = insertelement <8 x i16> undef, i16 %val_4.i21290, i32 444 %val_5.i21294 = load i16, ptr undef, align 245 %3 = insertelement <8 x i16> %2, i16 %val_5.i21294, i32 546 %val_6.i21298 = load i16, ptr undef, align 247 %4 = insertelement <8 x i16> %3, i16 %val_6.i21298, i32 648 %ptr_7.i21301 = inttoptr i64 undef to ptr49 %val_7.i21302 = load i16, ptr %ptr_7.i21301, align 250 %5 = insertelement <8 x i16> %4, i16 %val_7.i21302, i32 751 %uint2uint32.i20218 = zext <8 x i16> %5 to <8 x i32>52 %structelement561 = load ptr, ptr undef, align 853 %ptr2int563 = ptrtoint ptr %structelement561 to i6454 %smear.ptr_smear7571 = insertelement <8 x i64> undef, i64 %ptr2int563, i32 755 %new_ptr582 = add <8 x i64> %smear.ptr_smear7571, zeroinitializer56 %val_5.i21509 = load i8, ptr null, align 157 %6 = insertelement <8 x i8> undef, i8 %val_5.i21509, i32 558 %7 = insertelement <8 x i8> %6, i8 undef, i32 659 %iptr_7.i21515 = extractelement <8 x i64> %new_ptr582, i32 760 %ptr_7.i21516 = inttoptr i64 %iptr_7.i21515 to ptr61 %val_7.i21517 = load i8, ptr %ptr_7.i21516, align 162 %8 = insertelement <8 x i8> %7, i8 %val_7.i21517, i32 763 %uint2float.i20245 = uitofp <8 x i8> %8 to <8 x float>64 %binop.i20246 = fmul <8 x float> %uint2float.i20245, <float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000>65 br i1 undef, label %for_loop594.lr.ph, label %for_exit59566 67if_exit: ; preds = %if_else68 ret void69 70for_loop594.lr.ph: ; preds = %for_loop156.lr.ph71 %bitop8.i20221 = and <8 x i32> %uint2uint32.i20218, <i32 1023, i32 1023, i32 1023, i32 1023, i32 1023, i32 1023, i32 1023, i32 1023>72 br i1 undef, label %cif_test_all730, label %cif_mask_mixed155273 74for_exit595: ; preds = %for_loop156.lr.ph75 unreachable76 77cif_test_all730: ; preds = %for_loop594.lr.ph78 %binop11.i20545 = fmul <8 x float> %binop408, zeroinitializer79 %binop12.i20546 = fadd <8 x float> undef, %binop11.i2054580 %binop15.i20547 = fmul <8 x float> %binop411, undef81 %binop16.i20548 = fadd <8 x float> %binop12.i20546, %binop15.i2054782 %bincmp774 = fcmp ogt <8 x float> %binop16.i20548, zeroinitializer83 %val_to_boolvec32775 = sext <8 x i1> %bincmp774 to <8 x i32>84 %floatmask.i20549 = bitcast <8 x i32> %val_to_boolvec32775 to <8 x float>85 %v.i20550 = tail call i32 @llvm.x86.avx.movmsk.ps.256(<8 x float> %floatmask.i20549) nounwind readnone86 %cond = icmp eq i32 %v.i20550, 25587 br i1 %cond, label %cif_test_all794, label %cif_test_mixed88 89cif_test_all794: ; preds = %cif_test_all73090 %binop.i20572 = fmul <8 x float> %binop403, undef91 unreachable92 93cif_test_mixed: ; preds = %cif_test_all73094 %binop1207 = fmul <8 x float> %binop.i20246, undef95 unreachable96 97cif_mask_mixed1552: ; preds = %for_loop594.lr.ph98 unreachable99}100