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1; RUN: llc < %s -mtriple=x86_64-- -mcpu=corei7-avx -mattr=+avx2; Various missing patterns causing crashes.3; rdar://105387934 5define void @t1() nounwind {6entry:7 br label %loop.cond8 9loop.cond: ; preds = %t1.exit, %entry10 br i1 false, label %return, label %loop11 12loop: ; preds = %loop.cond13 br i1 undef, label %0, label %t1.exit14 15; <label>:0 ; preds = %loop16 %1 = load <16 x i32>, ptr addrspace(1) undef, align 6417 %2 = shufflevector <16 x i32> <i32 0, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>, <16 x i32> %1, <16 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 16, i32 0, i32 0>18 store <16 x i32> %2, ptr addrspace(1) undef, align 6419 br label %t1.exit20 21t1.exit: ; preds = %0, %loop22 br label %loop.cond23 24return: ; preds = %loop.cond25 ret void26}27 28define void @t2() nounwind {29 br i1 undef, label %1, label %430 31; <label>:1 ; preds = %032 %2 = load <16 x i32>, ptr addrspace(1) undef, align 6433 %3 = shufflevector <16 x i32> <i32 0, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>, <16 x i32> %2, <16 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 20, i32 0, i32 0, i32 0, i32 0>34 store <16 x i32> %3, ptr addrspace(1) undef, align 6435 br label %436 37; <label>:4 ; preds = %1, %038 ret void39}40 41define void @t3() nounwind {42entry:43 br label %loop.cond44 45loop.cond: ; preds = %t2.exit, %entry46 br i1 false, label %return, label %loop47 48loop: ; preds = %loop.cond49 br i1 undef, label %0, label %t2.exit50 51; <label>:0 ; preds = %loop52 %1 = shufflevector <16 x i32> <i32 0, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>, <16 x i32> undef, <16 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 25, i32 0>53 %2 = load <16 x i32>, ptr addrspace(1) undef, align 6454 %3 = shufflevector <16 x i32> <i32 0, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>, <16 x i32> %2, <16 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 28, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>55 store <16 x i32> %3, ptr addrspace(1) undef, align 6456 br label %t2.exit57 58t2.exit: ; preds = %0, %loop59 br label %loop.cond60 61return: ; preds = %loop.cond62 ret void63}64 65define <3 x i64> @t4() nounwind {66entry:67 %0 = load <2 x i64>, ptr addrspace(1) undef, align 1668 %1 = extractelement <2 x i64> %0, i32 069 %2 = insertelement <3 x i64> <i64 undef, i64 0, i64 0>, i64 %1, i32 070 ret <3 x i64> %271}72 73define void @t5() nounwind {74entry:75 %0 = shufflevector <2 x i64> zeroinitializer, <2 x i64> undef, <8 x i32> <i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>76 %1 = shufflevector <8 x i64> <i64 0, i64 0, i64 0, i64 undef, i64 undef, i64 0, i64 0, i64 0>, <8 x i64> %0, <8 x i32> <i32 0, i32 1, i32 2, i32 9, i32 8, i32 5, i32 6, i32 7>77 store <8 x i64> %1, ptr addrspace(1) undef, align 6478 79 ret void80}81