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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s3; rdar://75277344 5define i32 @test1(i32 %x) nounwind ssp {6; CHECK-LABEL: test1:7; CHECK: # %bb.0:8; CHECK-NEXT: # kill: def $edi killed $edi def $rdi9; CHECK-NEXT: shll $5, %edi10; CHECK-NEXT: leal 3(%rdi), %eax11; CHECK-NEXT: retq12 %t0 = shl i32 %x, 513 %t1 = or i32 %t0, 314 ret i32 %t115}16 17; This test no longer requires or to be converted to 3 addr form because we are18; are able to use a zero extend instead of an 'and' which gives the register19; allocator freedom.20define i64 @test2(i8 %A, i8 %B) nounwind {21; CHECK-LABEL: test2:22; CHECK: # %bb.0:23; CHECK-NEXT: shll $4, %edi24; CHECK-NEXT: andl $48, %edi25; CHECK-NEXT: movzbl %sil, %eax26; CHECK-NEXT: shrl $4, %eax27; CHECK-NEXT: orl %edi, %eax28; CHECK-NEXT: retq29 %C = zext i8 %A to i6430 %D = shl i64 %C, 431 %E = and i64 %D, 4832 %F = zext i8 %B to i6433 %G = lshr i64 %F, 434 %H = or i64 %G, %E35 ret i64 %H36}37 38;; Test that OR is only emitted as LEA, not as ADD.39 40; No reason to emit an add here, should be an or.41define void @test3(i32 %x, ptr %P) nounwind readnone ssp {42; CHECK-LABEL: test3:43; CHECK: # %bb.0:44; CHECK-NEXT: shll $5, %edi45; CHECK-NEXT: orl $3, %edi46; CHECK-NEXT: movl %edi, (%rsi)47; CHECK-NEXT: retq48 %t0 = shl i32 %x, 549 %t1 = or i32 %t0, 350 store i32 %t1, ptr %P51 ret void52}53 54define i32 @test4(i32 %a, i32 %b) nounwind readnone ssp {55; CHECK-LABEL: test4:56; CHECK: # %bb.0:57; CHECK-NEXT: # kill: def $esi killed $esi def $rsi58; CHECK-NEXT: # kill: def $edi killed $edi def $rdi59; CHECK-NEXT: andl $6, %edi60; CHECK-NEXT: andl $16, %esi61; CHECK-NEXT: leal (%rsi,%rdi), %eax62; CHECK-NEXT: retq63 %and = and i32 %a, 664 %and2 = and i32 %b, 1665 %or = or i32 %and2, %and66 ret i32 %or67}68 69define void @test5(i32 %a, i32 %b, ptr nocapture %P) nounwind ssp {70; CHECK-LABEL: test5:71; CHECK: # %bb.0:72; CHECK-NEXT: andl $6, %edi73; CHECK-NEXT: andl $16, %esi74; CHECK-NEXT: orl %edi, %esi75; CHECK-NEXT: movl %esi, (%rdx)76; CHECK-NEXT: retq77 %and = and i32 %a, 678 %and2 = and i32 %b, 1679 %or = or i32 %and2, %and80 store i32 %or, ptr %P, align 481 ret void82}83 84