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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=x86_64-- -mattr=+amx-tile -run-pass=fastpretileconfig -o - %s | FileCheck %s3#4# bb.05# def %06# / \7# bb.1 |-->bb.2 <-----------8# | %2=phi(%0, %3, %4) |9# def %1 -- %5=phi(%0, %3, %2) |10# \ / |11# bb.3 ---------------------12# def %313#14# This case test tile PHIs depend each other, and the its def block is15# not visited yet.16---17name: foo18alignment: 1619tracksRegLiveness: true20registers:21 - { id: 1, class: tile }22 - { id: 2, class: tile }23 - { id: 3, class: tile }24 - { id: 4, class: tile }25 - { id: 12, class: gr32 }26 - { id: 13, class: gr32 }27 - { id: 16, class: gr8 }28 - { id: 17, class: gr16 }29 - { id: 18, class: gr16 }30 - { id: 19, class: gr64_nosp }31 - { id: 22, class: gr32 }32 - { id: 23, class: gr16 }33 - { id: 24, class: gr16 }34liveins:35 - { reg: '$edi', virtual-reg: '%12' }36frameInfo:37 maxAlignment: 138machineFunctionInfo:39 amxProgModel: ManagedRA40body: |41 ; CHECK-LABEL: name: foo42 ; CHECK: bb.0.entry:43 ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)44 ; CHECK-NEXT: liveins: $edi45 ; CHECK-NEXT: {{ $}}46 ; CHECK-NEXT: [[V_SET0_:%[0-9]+]]:vr128 = V_SET047 ; CHECK-NEXT: MOVUPSmr %stack.1, 1, $noreg, 0, $noreg, [[V_SET0_]] :: (store (s512) into %stack.1, align 4)48 ; CHECK-NEXT: MOVUPSmr %stack.1, 1, $noreg, 16, $noreg, [[V_SET0_]] :: (store (s512) into %stack.1 + 16, align 4)49 ; CHECK-NEXT: MOVUPSmr %stack.1, 1, $noreg, 32, $noreg, [[V_SET0_]] :: (store (s512) into %stack.1 + 32, align 4)50 ; CHECK-NEXT: MOVUPSmr %stack.1, 1, $noreg, 48, $noreg, [[V_SET0_]] :: (store (s512) into %stack.1 + 48, align 4)51 ; CHECK-NEXT: MOV8mi %stack.1, 1, $noreg, 0, $noreg, 1 :: (store (s512) into %stack.1, align 4)52 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi53 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY killed [[COPY]]54 ; CHECK-NEXT: %r0:gr16 = MOV16ri 6455 ; CHECK-NEXT: %c0:gr16 = MOV16ri 1656 ; CHECK-NEXT: PLDTILECFGV %stack.1, 1, $noreg, 0, $noreg, implicit-def $tmm0, implicit-def $tmm1, implicit-def $tmm2, implicit-def $tmm3, implicit-def $tmm4, implicit-def $tmm5, implicit-def $tmm6, implicit-def $tmm7 :: (load (s512) from %stack.1, align 4)57 ; CHECK-NEXT: [[LEA64r:%[0-9]+]]:gr64_nosp = LEA64r %stack.0, 1, $noreg, 0, $noreg58 ; CHECK-NEXT: [[LEA64r1:%[0-9]+]]:gr64_nosp = LEA64r %stack.0, 1, $noreg, 0, $noreg59 ; CHECK-NEXT: %t0:tile = PTILEZEROV %r0, %c060 ; CHECK-NEXT: [[MOV64ri:%[0-9]+]]:gr64_nosp = MOV64ri 6461 ; CHECK-NEXT: TILESTORED %stack.0, 1, killed [[MOV64ri]], 0, $noreg, %t0 :: (store (s8192) into %stack.0)62 ; CHECK-NEXT: CMP32ri8 [[COPY1]], 0, implicit-def $eflags63 ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags64 ; CHECK-NEXT: TEST8ri [[SETCCr]], 1, implicit-def $eflags65 ; CHECK-NEXT: JCC_1 %bb.2, 5, implicit $eflags66 ; CHECK-NEXT: {{ $}}67 ; CHECK-NEXT: bb.1:68 ; CHECK-NEXT: successors: %bb.3(0x80000000)69 ; CHECK-NEXT: {{ $}}70 ; CHECK-NEXT: [[MOV16ri:%[0-9]+]]:gr16 = MOV16ri 6471 ; CHECK-NEXT: [[MOV16ri1:%[0-9]+]]:gr16 = MOV16ri 1672 ; CHECK-NEXT: PLDTILECFGV %stack.1, 1, $noreg, 0, $noreg, implicit-def $tmm0, implicit-def $tmm1, implicit-def $tmm2, implicit-def $tmm3, implicit-def $tmm4, implicit-def $tmm5, implicit-def $tmm6, implicit-def $tmm7 :: (load (s512) from %stack.1, align 4)73 ; CHECK-NEXT: [[PTILEZEROV:%[0-9]+]]:tile = PTILEZEROV killed [[MOV16ri1]], killed [[MOV16ri]]74 ; CHECK-NEXT: JMP_1 %bb.375 ; CHECK-NEXT: {{ $}}76 ; CHECK-NEXT: bb.2:77 ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000)78 ; CHECK-NEXT: {{ $}}79 ; CHECK-NEXT: [[PHI:%[0-9]+]]:gr16 = PHI %c0, %bb.0, %11, %bb.3, %17, %bb.280 ; CHECK-NEXT: [[PHI1:%[0-9]+]]:gr16 = PHI %r0, %bb.0, %12, %bb.3, %18, %bb.281 ; CHECK-NEXT: [[PHI2:%[0-9]+]]:gr64_nosp = PHI [[LEA64r1]], %bb.0, %31, %bb.3, %32, %bb.282 ; CHECK-NEXT: [[PHI3:%[0-9]+]]:gr16 = PHI %c0, %bb.0, %11, %bb.3, %17, %bb.283 ; CHECK-NEXT: [[PHI4:%[0-9]+]]:gr16 = PHI %r0, %bb.0, %12, %bb.3, %18, %bb.284 ; CHECK-NEXT: [[PHI5:%[0-9]+]]:gr64_nosp = PHI [[LEA64r]], %bb.0, %24, %bb.3, %25, %bb.285 ; CHECK-NEXT: PLDTILECFGV %stack.1, 1, $noreg, 0, $noreg, implicit-def $tmm0, implicit-def $tmm1, implicit-def $tmm2, implicit-def $tmm3, implicit-def $tmm4, implicit-def $tmm5, implicit-def $tmm6, implicit-def $tmm7 :: (load (s512) from %stack.1, align 4)86 ; CHECK-NEXT: [[MOV64ri1:%[0-9]+]]:gr64_nosp = MOV64ri 6487 ; CHECK-NEXT: [[PTILELOADDV:%[0-9]+]]:tile = PTILELOADDV [[PHI1]], [[PHI]], [[PHI2]], 1, killed [[MOV64ri1]], 0, $noreg88 ; CHECK-NEXT: [[MOV64ri2:%[0-9]+]]:gr64_nosp = MOV64ri 6489 ; CHECK-NEXT: [[PTILELOADDV1:%[0-9]+]]:tile = PTILELOADDV [[PHI4]], [[PHI3]], [[PHI5]], 1, killed [[MOV64ri2]], 0, $noreg90 ; CHECK-NEXT: [[MOV16ri2:%[0-9]+]]:gr16 = MOV16ri 6491 ; CHECK-NEXT: [[MOV16ri3:%[0-9]+]]:gr16 = MOV16ri 1692 ; CHECK-NEXT: PLDTILECFGV %stack.1, 1, $noreg, 0, $noreg, implicit-def $tmm0, implicit-def $tmm1, implicit-def $tmm2, implicit-def $tmm3, implicit-def $tmm4, implicit-def $tmm5, implicit-def $tmm6, implicit-def $tmm7 :: (load (s512) from %stack.1, align 4)93 ; CHECK-NEXT: [[LEA64r2:%[0-9]+]]:gr64_nosp = LEA64r %stack.3, 1, $noreg, 0, $noreg94 ; CHECK-NEXT: [[LEA64r3:%[0-9]+]]:gr64_nosp = LEA64r %stack.3, 1, $noreg, 0, $noreg95 ; CHECK-NEXT: [[PTILEZEROV1:%[0-9]+]]:tile = PTILEZEROV [[MOV16ri3]], [[MOV16ri2]]96 ; CHECK-NEXT: [[MOV64ri3:%[0-9]+]]:gr64_nosp = MOV64ri 6497 ; CHECK-NEXT: TILESTORED %stack.3, 1, killed [[MOV64ri3]], 0, $noreg, [[PTILEZEROV1]] :: (store (s8192) into %stack.3)98 ; CHECK-NEXT: TEST8ri [[SETCCr]], 1, implicit-def $eflags99 ; CHECK-NEXT: JCC_1 %bb.2, 5, implicit $eflags100 ; CHECK-NEXT: {{ $}}101 ; CHECK-NEXT: bb.3:102 ; CHECK-NEXT: successors: %bb.2(0x80000000)103 ; CHECK-NEXT: {{ $}}104 ; CHECK-NEXT: [[MOV16ri4:%[0-9]+]]:gr16 = MOV16ri 64105 ; CHECK-NEXT: [[MOV16ri5:%[0-9]+]]:gr16 = MOV16ri 16106 ; CHECK-NEXT: PLDTILECFGV %stack.1, 1, $noreg, 0, $noreg, implicit-def $tmm0, implicit-def $tmm1, implicit-def $tmm2, implicit-def $tmm3, implicit-def $tmm4, implicit-def $tmm5, implicit-def $tmm6, implicit-def $tmm7 :: (load (s512) from %stack.1, align 4)107 ; CHECK-NEXT: [[LEA64r4:%[0-9]+]]:gr64_nosp = LEA64r %stack.2, 1, $noreg, 0, $noreg108 ; CHECK-NEXT: [[LEA64r5:%[0-9]+]]:gr64_nosp = LEA64r %stack.2, 1, $noreg, 0, $noreg109 ; CHECK-NEXT: [[PTILEZEROV2:%[0-9]+]]:tile = PTILEZEROV [[MOV16ri5]], [[MOV16ri4]]110 ; CHECK-NEXT: [[MOV64ri4:%[0-9]+]]:gr64_nosp = MOV64ri 64111 ; CHECK-NEXT: TILESTORED %stack.2, 1, killed [[MOV64ri4]], 0, $noreg, [[PTILEZEROV2]] :: (store (s8192) into %stack.2)112 ; CHECK-NEXT: JMP_1 %bb.2113 bb.0.entry:114 liveins: $edi115 116 %12:gr32 = COPY $edi117 %13:gr32 = COPY killed %12118 %r0:gr16 = MOV16ri 64119 %c0:gr16 = MOV16ri 16120 %t0:tile = PTILEZEROV %r0, %c0121 CMP32ri8 %13, 0, implicit-def $eflags122 %16:gr8 = SETCCr 4, implicit $eflags123 TEST8ri %16, 1, implicit-def $eflags124 JCC_1 %bb.2, 5, implicit $eflags125 126 bb.1:127 %17:gr16 = MOV16ri 64128 %18:gr16 = MOV16ri 16129 %1:tile = PTILEZEROV killed %18, killed %17130 JMP_1 %bb.3131 132 bb.2:133 %2:tile = PHI %t0, %bb.0, %3, %bb.3, %4, %bb.2134 %5:tile = PHI %t0, %bb.0, %3, %bb.3, %2, %bb.2135 %25:gr16 = MOV16ri 64136 %26:gr16 = MOV16ri 16137 %4:tile = PTILEZEROV killed %26, killed %25138 TEST8ri %16, 1, implicit-def $eflags139 JCC_1 %bb.2, 5, implicit $eflags140 141 bb.3:142 %23:gr16 = MOV16ri 64143 %24:gr16 = MOV16ri 16144 %3:tile = PTILEZEROV killed %24, killed %23145 JMP_1 %bb.2146