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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=x86_64-- -mattr=+amx-int8,avx512f -run-pass=fastpretileconfig -o - %s | FileCheck %s3 4# Test the case which has TILELOADD being mixed in pseudo AMX instruction5...6---7name: main8alignment: 169tracksRegLiveness: true10registers:11 - { id: 0, class: gr64_nosp }12 - { id: 1, class: gr64 }13 - { id: 2, class: gr16 }14 - { id: 3, class: gr16 }15 - { id: 4, class: tile }16 - { id: 5, class: tile }17 - { id: 6, class: tile }18 - { id: 7, class: tile }19 - { id: 8, class: gr32 }20 - { id: 9, class: vr512 }21frameInfo:22 maxAlignment: 1623stack:24 - { id: 0, size: 1024, alignment: 16 }25 - { id: 1, size: 64, alignment: 4 }26machineFunctionInfo:27 amxProgModel: ManagedRA28body: |29 bb.0.entry:30 ; CHECK-LABEL: name: main31 ; CHECK: [[AVX512_512_SET0_:%[0-9]+]]:vr512 = AVX512_512_SET032 ; CHECK-NEXT: VMOVUPSZmr %stack.2, 1, $noreg, 0, $noreg, [[AVX512_512_SET0_]] :: (store (s512) into %stack.2, align 4)33 ; CHECK-NEXT: MOV8mi %stack.2, 1, $noreg, 0, $noreg, 1 :: (store (s512) into %stack.2, align 4)34 ; CHECK-NEXT: [[MOV32ri64_:%[0-9]+]]:gr64_nosp = MOV32ri64 3235 ; CHECK-NEXT: [[LEA64r:%[0-9]+]]:gr64 = LEA64r %stack.0, 1, $noreg, 0, $noreg36 ; CHECK-NEXT: [[MOV16ri:%[0-9]+]]:gr16 = MOV16ri 3237 ; CHECK-NEXT: [[MOV16ri1:%[0-9]+]]:gr16 = MOV16ri 838 ; CHECK-NEXT: PLDTILECFGV %stack.2, 1, $noreg, 0, $noreg, implicit-def $tmm0, implicit-def $tmm1, implicit-def $tmm2, implicit-def $tmm3, implicit-def $tmm4, implicit-def $tmm5, implicit-def $tmm6, implicit-def $tmm7 :: (load (s512) from %stack.2, align 4)39 ; CHECK-NEXT: $tmm0 = TILELOADD [[LEA64r]], 1, [[MOV32ri64_]], 0, $noreg40 ; CHECK-NEXT: [[PTILELOADDV:%[0-9]+]]:tile = PTILELOADDV [[MOV16ri1]], [[MOV16ri]], [[LEA64r]], 1, [[MOV32ri64_]], 0, $noreg41 ; CHECK-NEXT: [[PTILELOADDV1:%[0-9]+]]:tile = PTILELOADDV [[MOV16ri1]], [[MOV16ri]], [[LEA64r]], 1, [[MOV32ri64_]], 0, $noreg42 ; CHECK-NEXT: [[PTILELOADDV2:%[0-9]+]]:tile = PTILELOADDV [[MOV16ri1]], [[MOV16ri]], [[LEA64r]], 1, [[MOV32ri64_]], 0, $noreg43 ; CHECK-NEXT: [[PTDPBSSDV:%[0-9]+]]:tile = PTDPBSSDV [[MOV16ri1]], [[MOV16ri]], [[MOV16ri]], killed [[PTILELOADDV2]], killed [[PTILELOADDV]], killed [[PTILELOADDV1]]44 ; CHECK-NEXT: PTILESTOREDV killed [[MOV16ri1]], killed [[MOV16ri]], killed [[LEA64r]], 1, killed [[MOV32ri64_]], 0, $noreg, killed [[PTDPBSSDV]]45 ; CHECK-NEXT: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def dead $eflags46 ; CHECK-NEXT: $eax = COPY killed [[MOV32r0_]]47 ; CHECK-NEXT: RET 0, killed $eax48 %0:gr64_nosp = MOV32ri64 3249 %1:gr64 = LEA64r %stack.0, 1, $noreg, 0, $noreg50 %2:gr16 = MOV16ri 3251 %3:gr16 = MOV16ri 852 $tmm0 = TILELOADD %1, 1, %0, 0, $noreg53 %4:tile = PTILELOADDV %3, %2, %1, 1, %0, 0, $noreg54 %5:tile = PTILELOADDV %3, %2, %1, 1, %0, 0, $noreg55 %6:tile = PTILELOADDV %3, %2, %1, 1, %0, 0, $noreg56 %7:tile = PTDPBSSDV %3, %2, %2, killed %6, killed %4, killed %557 PTILESTOREDV killed %3, killed %2, killed %1, 1, killed %0, 0, $noreg, killed %758 %8:gr32 = MOV32r0 implicit-def dead $eflags59 $eax = COPY killed %860 RET 0, killed $eax61 62...63# GlobalIsel doesn't use all virtual registers and there may be virtual64# registers without a class.65# Note that %3 doesn't have a class: gpr instead of gr64.66---67name: test_unused68legalized: true69regBankSelected: true70selected: true71failedISel: false72tracksRegLiveness: true73registers:74 - { id: 0, class: gr64, preferred-register: '' }75 - { id: 1, class: gr64_with_sub_8bit, preferred-register: '' }76 - { id: 2, class: gr64, preferred-register: '' }77 - { id: 3, class: gpr, preferred-register: '' }78 - { id: 4, class: gr64, preferred-register: '' }79 - { id: 5, class: gr8, preferred-register: '' }80liveins:81 - { reg: '$rdi', virtual-reg: '' }82 - { reg: '$rsi', virtual-reg: '' }83machineFunctionInfo:84 amxProgModel: ManagedRA85body: |86 bb.1.entry:87 liveins: $rdi, $rsi88 89 ; CHECK-LABEL: name: test_unused90 ; CHECK: liveins: $rdi, $rsi91 ; CHECK-NEXT: {{ $}}92 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi93 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr64_with_sub_8bit = COPY $rsi94 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr8 = COPY [[COPY1]].sub_8bit95 ; CHECK-NEXT: $cl = COPY [[COPY2]]96 ; CHECK-NEXT: [[SHR64rCL:%[0-9]+]]:gr64 = SHR64rCL [[COPY]], implicit-def $eflags, implicit $cl97 ; CHECK-NEXT: [[ADD64ri32_:%[0-9]+]]:gr64 = ADD64ri32 [[SHR64rCL]], 123456789, implicit-def $eflags98 ; CHECK-NEXT: $rax = COPY [[ADD64ri32_]]99 ; CHECK-NEXT: RET 0, implicit $rax100 %0:gr64 = COPY $rdi101 %1:gr64_with_sub_8bit = COPY $rsi102 %5:gr8 = COPY %1.sub_8bit103 $cl = COPY %5104 %2:gr64 = SHR64rCL %0, implicit-def $eflags, implicit $cl105 %4:gr64 = ADD64ri32 %2, 123456789, implicit-def $eflags106 $rax = COPY %4107 RET 0, implicit $rax108 109...110