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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+amx-tile,+amx-int8,+amx-bf16,+avx512f -verify-machineinstrs | FileCheck %s3 4define void @test_amx(ptr %pointer, ptr %base, i64 %stride) {5; CHECK-LABEL: test_amx:6; CHECK: # %bb.0:7; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm08; CHECK-NEXT: vmovups %zmm0, -{{[0-9]+}}(%rsp)9; CHECK-NEXT: movb $1, -{{[0-9]+}}(%rsp)10; CHECK-NEXT: movb $8, -{{[0-9]+}}(%rsp)11; CHECK-NEXT: movw $8, -{{[0-9]+}}(%rsp)12; CHECK-NEXT: movb $8, -{{[0-9]+}}(%rsp)13; CHECK-NEXT: movw $8, -{{[0-9]+}}(%rsp)14; CHECK-NEXT: movb $8, -{{[0-9]+}}(%rsp)15; CHECK-NEXT: movw $8, -{{[0-9]+}}(%rsp)16; CHECK-NEXT: ldtilecfg -{{[0-9]+}}(%rsp)17; CHECK-NEXT: movw $8, %ax18; CHECK-NEXT: tilezero %tmm019; CHECK-NEXT: tileloadd (%rsi,%rdx), %tmm120; CHECK-NEXT: tileloadd (%rsi,%rdx), %tmm221; CHECK-NEXT: tdpbssd %tmm2, %tmm1, %tmm022; CHECK-NEXT: tdpbsud %tmm2, %tmm1, %tmm023; CHECK-NEXT: tdpbusd %tmm2, %tmm1, %tmm024; CHECK-NEXT: tdpbuud %tmm2, %tmm1, %tmm025; CHECK-NEXT: tdpbf16ps %tmm2, %tmm1, %tmm026; CHECK-NEXT: tileloaddt1 (%rsi,%rdx), %tmm127; CHECK-NEXT: tilestored %tmm0, (%rdi,%rdx)28; CHECK-NEXT: tilerelease29; CHECK-NEXT: vzeroupper30; CHECK-NEXT: retq31 %c = call x86_amx @llvm.x86.tilezero.internal(i16 8, i16 8)32 %a = call x86_amx @llvm.x86.tileloadd64.internal(i16 8, i16 8, ptr %base, i64 %stride)33 %b = call x86_amx @llvm.x86.tileloadd64.internal(i16 8, i16 8, ptr %base, i64 %stride)34 %d0 = call x86_amx @llvm.x86.tdpbssd.internal(i16 8, i16 8, i16 8, x86_amx %c, x86_amx %a, x86_amx %b)35 %d1 = call x86_amx @llvm.x86.tdpbsud.internal(i16 8, i16 8, i16 8, x86_amx %d0, x86_amx %a, x86_amx %b)36 %d2 = call x86_amx @llvm.x86.tdpbusd.internal(i16 8, i16 8, i16 8, x86_amx %d1, x86_amx %a, x86_amx %b)37 %d3 = call x86_amx @llvm.x86.tdpbuud.internal(i16 8, i16 8, i16 8, x86_amx %d2, x86_amx %a, x86_amx %b)38 %d4 = call x86_amx @llvm.x86.tdpbf16ps.internal(i16 8, i16 8, i16 8, x86_amx %d3, x86_amx %a, x86_amx %b)39 %e = call x86_amx @llvm.x86.tileloaddt164.internal(i16 8, i16 8, ptr %base, i64 %stride)40 call void @llvm.x86.tilestored64.internal(i16 8, i16 8, ptr %pointer, i64 %stride, x86_amx %d4)41 42 ret void43}44 45declare x86_amx @llvm.x86.tilezero.internal(i16, i16)46declare x86_amx @llvm.x86.tileloadd64.internal(i16, i16, ptr, i64)47declare x86_amx @llvm.x86.tileloaddt164.internal(i16, i16, ptr, i64)48declare x86_amx @llvm.x86.tdpbssd.internal(i16, i16, i16, x86_amx, x86_amx, x86_amx)49declare x86_amx @llvm.x86.tdpbsud.internal(i16, i16, i16, x86_amx, x86_amx, x86_amx)50declare x86_amx @llvm.x86.tdpbusd.internal(i16, i16, i16, x86_amx, x86_amx, x86_amx)51declare x86_amx @llvm.x86.tdpbuud.internal(i16, i16, i16, x86_amx, x86_amx, x86_amx)52declare x86_amx @llvm.x86.tdpbf16ps.internal(i16, i16, i16, x86_amx, x86_amx, x86_amx)53declare void @llvm.x86.tilestored64.internal(i16, i16, ptr, i64, x86_amx)54 55define void @PR90954(ptr %0, ptr %1, i32 %2) nounwind {56; CHECK-LABEL: PR90954:57; CHECK: # %bb.0:58; CHECK-NEXT: pushq %rbp59; CHECK-NEXT: pushq %r1460; CHECK-NEXT: pushq %rbx61; CHECK-NEXT: subq $2912, %rsp # imm = 0xB6062; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm063; CHECK-NEXT: vmovups %zmm0, {{[0-9]+}}(%rsp)64; CHECK-NEXT: movb $1, {{[0-9]+}}(%rsp)65; CHECK-NEXT: movb $16, {{[0-9]+}}(%rsp)66; CHECK-NEXT: movw $64, {{[0-9]+}}(%rsp)67; CHECK-NEXT: movb $16, {{[0-9]+}}(%rsp)68; CHECK-NEXT: movw $64, {{[0-9]+}}(%rsp)69; CHECK-NEXT: movb $16, {{[0-9]+}}(%rsp)70; CHECK-NEXT: movw $64, {{[0-9]+}}(%rsp)71; CHECK-NEXT: ldtilecfg {{[0-9]+}}(%rsp)72; CHECK-NEXT: shll $4, %edx73; CHECK-NEXT: xorl %eax, %eax74; CHECK-NEXT: movw $64, %cx75; CHECK-NEXT: movw $16, %di76; CHECK-NEXT: movb $1, %r8b77; CHECK-NEXT: xorl %r9d, %r9d78; CHECK-NEXT: xorl %r10d, %r10d79; CHECK-NEXT: jmp .LBB1_180; CHECK-NEXT: .p2align 481; CHECK-NEXT: .LBB1_5: # in Loop: Header=BB1_1 Depth=182; CHECK-NEXT: incq %r1083; CHECK-NEXT: addl %edx, %r9d84; CHECK-NEXT: .LBB1_1: # =>This Loop Header: Depth=185; CHECK-NEXT: # Child Loop BB1_2 Depth 286; CHECK-NEXT: movslq %r9d, %r1187; CHECK-NEXT: leaq (%rsi,%r11,4), %r1188; CHECK-NEXT: xorl %ebx, %ebx89; CHECK-NEXT: xorl %r14d, %r14d90; CHECK-NEXT: jmp .LBB1_291; CHECK-NEXT: .p2align 492; CHECK-NEXT: .LBB1_4: # in Loop: Header=BB1_2 Depth=293; CHECK-NEXT: tilestored %tmm1, (%r11,%rax)94; CHECK-NEXT: incq %r1495; CHECK-NEXT: addq $64, %r1196; CHECK-NEXT: decq %rbx97; CHECK-NEXT: je .LBB1_598; CHECK-NEXT: .LBB1_2: # Parent Loop BB1_1 Depth=199; CHECK-NEXT: # => This Inner Loop Header: Depth=2100; CHECK-NEXT: tilezero %tmm0101; CHECK-NEXT: tilezero %tmm1102; CHECK-NEXT: testb %r8b, %r8b103; CHECK-NEXT: jne .LBB1_4104; CHECK-NEXT: # %bb.3: # in Loop: Header=BB1_2 Depth=2105; CHECK-NEXT: tilezero %tmm1106; CHECK-NEXT: tilezero %tmm2107; CHECK-NEXT: tdpbf16ps %tmm2, %tmm1, %tmm0108; CHECK-NEXT: movabsq $64, %rbp109; CHECK-NEXT: tilestored %tmm0, 896(%rsp,%rbp) # 1024-byte Folded Spill110; CHECK-NEXT: tileloadd 896(%rsp,%rbp), %tmm1 # 1024-byte Folded Reload111; CHECK-NEXT: jmp .LBB1_4112 %4 = shl i32 %2, 4113 %5 = icmp eq i64 0, 0114 br label %6115 1166: ; preds = %31, %3117 %7 = phi i64 [ 0, %3 ], [ %32, %31 ]118 %8 = trunc nuw nsw i64 %7 to i32119 %9 = mul i32 %4, %8120 %10 = mul i32 0, %8121 %11 = sext i32 %9 to i64122 %12 = getelementptr inbounds i32, ptr %1, i64 %11123 br label %13124 12513: ; preds = %25, %6126 %14 = phi i64 [ %29, %25 ], [ 0, %6 ]127 %15 = tail call x86_amx @llvm.x86.tilezero.internal(i16 16, i16 64)128 %16 = tail call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx %15)129 %17 = shl nsw i64 %14, 4130 %18 = getelementptr i32, ptr %0, i64 %17131 br i1 %5, label %25, label %19132 13319: ; preds = %13134 %20 = tail call x86_amx @llvm.x86.cast.vector.to.tile.v256i32(<256 x i32> %16)135 %21 = tail call x86_amx @llvm.x86.cast.vector.to.tile.v256i32(<256 x i32> zeroinitializer)136 %22 = tail call x86_amx @llvm.x86.cast.vector.to.tile.v256i32(<256 x i32> zeroinitializer)137 %23 = tail call x86_amx @llvm.x86.tdpbf16ps.internal(i16 16, i16 64, i16 64, x86_amx %20, x86_amx %21, x86_amx %22)138 %24 = tail call noundef <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx %23)139 br label %25140 14125: ; preds = %19, %13142 %26 = phi <256 x i32> [ undef, %13 ], [ %24, %19 ]143 %27 = getelementptr inbounds i32, ptr %12, i64 %17144 %28 = tail call x86_amx @llvm.x86.cast.vector.to.tile.v256i32(<256 x i32> %26)145 tail call void @llvm.x86.tilestored64.internal(i16 16, i16 64, ptr %27, i64 0, x86_amx %28)146 %29 = add nuw nsw i64 %14, 1147 %30 = icmp eq i64 %29, 0148 br i1 %30, label %31, label %13149 15031: ; preds = %25151 %32 = add nuw nsw i64 %7, 1152 br label %6153}154 155define void @multi_use() nounwind {156; CHECK-LABEL: multi_use:157; CHECK: # %bb.0:158; CHECK-NEXT: pushq %rbp159; CHECK-NEXT: subq $2928, %rsp # imm = 0xB70160; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0161; CHECK-NEXT: vmovups %zmm0, {{[0-9]+}}(%rsp)162; CHECK-NEXT: movb $1, {{[0-9]+}}(%rsp)163; CHECK-NEXT: movb $16, {{[0-9]+}}(%rsp)164; CHECK-NEXT: movw $64, {{[0-9]+}}(%rsp)165; CHECK-NEXT: movb $16, {{[0-9]+}}(%rsp)166; CHECK-NEXT: movw $64, {{[0-9]+}}(%rsp)167; CHECK-NEXT: movw $64, %ax168; CHECK-NEXT: ldtilecfg {{[0-9]+}}(%rsp)169; CHECK-NEXT: movw $16, %cx170; CHECK-NEXT: tilezero %tmm0171; CHECK-NEXT: movabsq $64, %rbp172; CHECK-NEXT: tilestored %tmm0, 896(%rsp,%rbp) # 1024-byte Folded Spill173; CHECK-NEXT: tileloadd 896(%rsp,%rbp), %tmm1 # 1024-byte Folded Reload174; CHECK-NEXT: tdpbf16ps %tmm0, %tmm0, %tmm1175; CHECK-NEXT: tdpbf16ps %tmm0, %tmm0, %tmm0176; CHECK-NEXT: addq $2928, %rsp # imm = 0xB70177; CHECK-NEXT: popq %rbp178; CHECK-NEXT: tilerelease179; CHECK-NEXT: vzeroupper180; CHECK-NEXT: retq181 %1 = call x86_amx @llvm.x86.tilezero.internal(i16 16, i16 64)182 %2 = call x86_amx @llvm.x86.tdpbf16ps.internal(i16 16, i16 64, i16 64, x86_amx %1, x86_amx %1, x86_amx %1)183 %3 = call x86_amx @llvm.x86.tdpbf16ps.internal(i16 16, i16 64, i16 64, x86_amx %1, x86_amx %1, x86_amx %1)184 ret void185}186 187declare x86_amx @llvm.x86.cast.vector.to.tile.v256i32(<256 x i32>)188declare <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx)189