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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=x86_64-linux-gnu -global-isel -verify-machineinstrs < %s -o - | FileCheck %s --check-prefixes=CHECK,SSE3; RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -global-isel -verify-machineinstrs < %s -o - | FileCheck %s --check-prefixes=CHECK,AVX4; RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -global-isel -verify-machineinstrs < %s -o - | FileCheck %s --check-prefixes=CHECK,AVX5; RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -mattr=+avx512vl -global-isel -verify-machineinstrs < %s -o - | FileCheck %s --check-prefixes=CHECK,AVX6 7define i64 @test_sub_i64(i64 %arg1, i64 %arg2) {8; CHECK-LABEL: test_sub_i64:9; CHECK: # %bb.0:10; CHECK-NEXT: movq %rdi, %rax11; CHECK-NEXT: subq %rsi, %rax12; CHECK-NEXT: retq13 %ret = sub i64 %arg1, %arg214 ret i64 %ret15}16 17define i32 @test_sub_i32(i32 %arg1, i32 %arg2) {18; CHECK-LABEL: test_sub_i32:19; CHECK: # %bb.0:20; CHECK-NEXT: movl %edi, %eax21; CHECK-NEXT: subl %esi, %eax22; CHECK-NEXT: retq23 %ret = sub i32 %arg1, %arg224 ret i32 %ret25}26 27define float @test_add_float(float %arg1, float %arg2) {28; SSE-LABEL: test_add_float:29; SSE: # %bb.0:30; SSE-NEXT: addss %xmm1, %xmm031; SSE-NEXT: retq32;33; AVX-LABEL: test_add_float:34; AVX: # %bb.0:35; AVX-NEXT: vaddss %xmm1, %xmm0, %xmm036; AVX-NEXT: retq37 %ret = fadd float %arg1, %arg238 ret float %ret39}40 41define double @test_add_double(double %arg1, double %arg2) {42; SSE-LABEL: test_add_double:43; SSE: # %bb.0:44; SSE-NEXT: addsd %xmm1, %xmm045; SSE-NEXT: retq46;47; AVX-LABEL: test_add_double:48; AVX: # %bb.0:49; AVX-NEXT: vaddsd %xmm1, %xmm0, %xmm050; AVX-NEXT: retq51 %ret = fadd double %arg1, %arg252 ret double %ret53}54 55define float @test_sub_float(float %arg1, float %arg2) {56; SSE-LABEL: test_sub_float:57; SSE: # %bb.0:58; SSE-NEXT: subss %xmm1, %xmm059; SSE-NEXT: retq60;61; AVX-LABEL: test_sub_float:62; AVX: # %bb.0:63; AVX-NEXT: vsubss %xmm1, %xmm0, %xmm064; AVX-NEXT: retq65 %ret = fsub float %arg1, %arg266 ret float %ret67}68 69define double @test_sub_double(double %arg1, double %arg2) {70; SSE-LABEL: test_sub_double:71; SSE: # %bb.0:72; SSE-NEXT: subsd %xmm1, %xmm073; SSE-NEXT: retq74;75; AVX-LABEL: test_sub_double:76; AVX: # %bb.0:77; AVX-NEXT: vsubsd %xmm1, %xmm0, %xmm078; AVX-NEXT: retq79 %ret = fsub double %arg1, %arg280 ret double %ret81}82 83define <4 x i32> @test_add_v4i32(<4 x i32> %arg1, <4 x i32> %arg2) {84; SSE-LABEL: test_add_v4i32:85; SSE: # %bb.0:86; SSE-NEXT: paddd %xmm1, %xmm087; SSE-NEXT: retq88;89; AVX-LABEL: test_add_v4i32:90; AVX: # %bb.0:91; AVX-NEXT: vpaddd %xmm1, %xmm0, %xmm092; AVX-NEXT: retq93 %ret = add <4 x i32> %arg1, %arg294 ret <4 x i32> %ret95}96 97define <4 x i32> @test_sub_v4i32(<4 x i32> %arg1, <4 x i32> %arg2) {98; SSE-LABEL: test_sub_v4i32:99; SSE: # %bb.0:100; SSE-NEXT: psubd %xmm1, %xmm0101; SSE-NEXT: retq102;103; AVX-LABEL: test_sub_v4i32:104; AVX: # %bb.0:105; AVX-NEXT: vpsubd %xmm1, %xmm0, %xmm0106; AVX-NEXT: retq107 %ret = sub <4 x i32> %arg1, %arg2108 ret <4 x i32> %ret109}110 111define <4 x float> @test_add_v4f32(<4 x float> %arg1, <4 x float> %arg2) {112; SSE-LABEL: test_add_v4f32:113; SSE: # %bb.0:114; SSE-NEXT: addps %xmm1, %xmm0115; SSE-NEXT: retq116;117; AVX-LABEL: test_add_v4f32:118; AVX: # %bb.0:119; AVX-NEXT: vaddps %xmm1, %xmm0, %xmm0120; AVX-NEXT: retq121 %ret = fadd <4 x float> %arg1, %arg2122 ret <4 x float> %ret123}124 125define <4 x float> @test_sub_v4f32(<4 x float> %arg1, <4 x float> %arg2) {126; SSE-LABEL: test_sub_v4f32:127; SSE: # %bb.0:128; SSE-NEXT: subps %xmm1, %xmm0129; SSE-NEXT: retq130;131; AVX-LABEL: test_sub_v4f32:132; AVX: # %bb.0:133; AVX-NEXT: vsubps %xmm1, %xmm0, %xmm0134; AVX-NEXT: retq135 %ret = fsub <4 x float> %arg1, %arg2136 ret <4 x float> %ret137}138 139define i32 @test_copy_float(float %val) {140; SSE-LABEL: test_copy_float:141; SSE: # %bb.0:142; SSE-NEXT: movd %xmm0, %eax143; SSE-NEXT: retq144;145; AVX-LABEL: test_copy_float:146; AVX: # %bb.0:147; AVX-NEXT: vmovd %xmm0, %eax148; AVX-NEXT: retq149 %r = bitcast float %val to i32150 ret i32 %r151}152 153define float @test_copy_i32(i32 %val) {154; SSE-LABEL: test_copy_i32:155; SSE: # %bb.0:156; SSE-NEXT: movd %edi, %xmm0157; SSE-NEXT: retq158;159; AVX-LABEL: test_copy_i32:160; AVX: # %bb.0:161; AVX-NEXT: vmovd %edi, %xmm0162; AVX-NEXT: retq163 %r = bitcast i32 %val to float164 ret float %r165}166 167