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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+sse2 -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=ALL3 4--- |5 define void @test_add_v16i8() {6 %ret = add <16 x i8> undef, undef7 ret void8 }9 10 define void @test_add_v8i16() {11 %ret = add <8 x i16> undef, undef12 ret void13 }14 15 define void @test_add_v4i32() {16 %ret = add <4 x i32> undef, undef17 ret void18 }19 20 define void @test_add_v2i64() {21 %ret = add <2 x i64> undef, undef22 ret void23 }24...25---26name: test_add_v16i827alignment: 1628legalized: false29regBankSelected: false30registers:31 - { id: 0, class: _ }32 - { id: 1, class: _ }33 - { id: 2, class: _ }34body: |35 bb.1 (%ir-block.0):36 liveins: $xmm0, $xmm137 38 ; ALL-LABEL: name: test_add_v16i839 ; ALL: liveins: $xmm0, $xmm140 ; ALL-NEXT: {{ $}}41 ; ALL-NEXT: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF42 ; ALL-NEXT: [[DEF1:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF43 ; ALL-NEXT: [[ADD:%[0-9]+]]:_(<16 x s8>) = G_ADD [[DEF]], [[DEF1]]44 ; ALL-NEXT: $xmm0 = COPY [[ADD]](<16 x s8>)45 ; ALL-NEXT: RET 046 %0(<16 x s8>) = IMPLICIT_DEF47 %1(<16 x s8>) = IMPLICIT_DEF48 %2(<16 x s8>) = G_ADD %0, %149 $xmm0 = COPY %250 RET 051 52...53---54name: test_add_v8i1655alignment: 1656legalized: false57regBankSelected: false58registers:59 - { id: 0, class: _ }60 - { id: 1, class: _ }61 - { id: 2, class: _ }62body: |63 bb.1 (%ir-block.0):64 liveins: $xmm0, $xmm165 66 ; ALL-LABEL: name: test_add_v8i1667 ; ALL: liveins: $xmm0, $xmm168 ; ALL-NEXT: {{ $}}69 ; ALL-NEXT: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF70 ; ALL-NEXT: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF71 ; ALL-NEXT: [[ADD:%[0-9]+]]:_(<8 x s16>) = G_ADD [[DEF]], [[DEF1]]72 ; ALL-NEXT: $xmm0 = COPY [[ADD]](<8 x s16>)73 ; ALL-NEXT: RET 074 %0(<8 x s16>) = IMPLICIT_DEF75 %1(<8 x s16>) = IMPLICIT_DEF76 %2(<8 x s16>) = G_ADD %0, %177 $xmm0 = COPY %278 RET 079 80...81---82name: test_add_v4i3283alignment: 1684legalized: false85regBankSelected: false86registers:87 - { id: 0, class: _ }88 - { id: 1, class: _ }89 - { id: 2, class: _ }90body: |91 bb.1 (%ir-block.0):92 liveins: $xmm0, $xmm193 94 ; ALL-LABEL: name: test_add_v4i3295 ; ALL: liveins: $xmm0, $xmm196 ; ALL-NEXT: {{ $}}97 ; ALL-NEXT: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF98 ; ALL-NEXT: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF99 ; ALL-NEXT: [[ADD:%[0-9]+]]:_(<4 x s32>) = G_ADD [[DEF]], [[DEF1]]100 ; ALL-NEXT: $xmm0 = COPY [[ADD]](<4 x s32>)101 ; ALL-NEXT: RET 0102 %0(<4 x s32>) = IMPLICIT_DEF103 %1(<4 x s32>) = IMPLICIT_DEF104 %2(<4 x s32>) = G_ADD %0, %1105 $xmm0 = COPY %2106 RET 0107 108...109---110name: test_add_v2i64111alignment: 16112legalized: false113regBankSelected: false114registers:115 - { id: 0, class: _ }116 - { id: 1, class: _ }117 - { id: 2, class: _ }118body: |119 bb.1 (%ir-block.0):120 liveins: $xmm0, $xmm1121 122 ; ALL-LABEL: name: test_add_v2i64123 ; ALL: liveins: $xmm0, $xmm1124 ; ALL-NEXT: {{ $}}125 ; ALL-NEXT: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF126 ; ALL-NEXT: [[DEF1:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF127 ; ALL-NEXT: [[ADD:%[0-9]+]]:_(<2 x s64>) = G_ADD [[DEF]], [[DEF1]]128 ; ALL-NEXT: $xmm0 = COPY [[ADD]](<2 x s64>)129 ; ALL-NEXT: RET 0130 %0(<2 x s64>) = IMPLICIT_DEF131 %1(<2 x s64>) = IMPLICIT_DEF132 %2(<2 x s64>) = G_ADD %0, %1133 $xmm0 = COPY %2134 RET 0135 136...137