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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=AVX13# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=AVX512F4# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f,+avx512bw -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=AVX512BW5 6# TODO: add tests for additional configuration after the legalization supported7 8--- |9 define void @test_add_v64i8() {10 %ret = add <64 x i8> undef, undef11 ret void12 }13 14 define void @test_add_v32i16() {15 %ret = add <32 x i16> undef, undef16 ret void17 }18 19 define void @test_add_v16i32() {20 %ret = add <16 x i32> undef, undef21 ret void22 }23 24 define void @test_add_v8i64() {25 %ret = add <8 x i64> undef, undef26 ret void27 }28 29 define <64 x i8> @test_add_v64i8_2(<64 x i8> %arg1, <64 x i8> %arg2) #0 {30 %ret = add <64 x i8> %arg1, %arg231 ret <64 x i8> %ret32 }33...34---35name: test_add_v64i836alignment: 1637legalized: false38regBankSelected: false39registers:40 - { id: 0, class: _ }41 - { id: 1, class: _ }42 - { id: 2, class: _ }43body: |44 bb.1 (%ir-block.0):45 liveins: $zmm0, $zmm146 47 ; AVX1-LABEL: name: test_add_v64i848 ; AVX1: liveins: $zmm0, $zmm149 ; AVX1-NEXT: {{ $}}50 ; AVX1-NEXT: [[DEF:%[0-9]+]]:_(<64 x s8>) = IMPLICIT_DEF51 ; AVX1-NEXT: [[DEF1:%[0-9]+]]:_(<64 x s8>) = IMPLICIT_DEF52 ; AVX1-NEXT: [[UV:%[0-9]+]]:_(<16 x s8>), [[UV1:%[0-9]+]]:_(<16 x s8>), [[UV2:%[0-9]+]]:_(<16 x s8>), [[UV3:%[0-9]+]]:_(<16 x s8>) = G_UNMERGE_VALUES [[DEF]](<64 x s8>)53 ; AVX1-NEXT: [[UV4:%[0-9]+]]:_(<16 x s8>), [[UV5:%[0-9]+]]:_(<16 x s8>), [[UV6:%[0-9]+]]:_(<16 x s8>), [[UV7:%[0-9]+]]:_(<16 x s8>) = G_UNMERGE_VALUES [[DEF1]](<64 x s8>)54 ; AVX1-NEXT: [[ADD:%[0-9]+]]:_(<16 x s8>) = G_ADD [[UV]], [[UV4]]55 ; AVX1-NEXT: [[ADD1:%[0-9]+]]:_(<16 x s8>) = G_ADD [[UV1]], [[UV5]]56 ; AVX1-NEXT: [[ADD2:%[0-9]+]]:_(<16 x s8>) = G_ADD [[UV2]], [[UV6]]57 ; AVX1-NEXT: [[ADD3:%[0-9]+]]:_(<16 x s8>) = G_ADD [[UV3]], [[UV7]]58 ; AVX1-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<64 x s8>) = G_CONCAT_VECTORS [[ADD]](<16 x s8>), [[ADD1]](<16 x s8>), [[ADD2]](<16 x s8>), [[ADD3]](<16 x s8>)59 ; AVX1-NEXT: $zmm0 = COPY [[CONCAT_VECTORS]](<64 x s8>)60 ; AVX1-NEXT: RET 061 ;62 ; AVX512F-LABEL: name: test_add_v64i863 ; AVX512F: liveins: $zmm0, $zmm164 ; AVX512F-NEXT: {{ $}}65 ; AVX512F-NEXT: [[DEF:%[0-9]+]]:_(<64 x s8>) = IMPLICIT_DEF66 ; AVX512F-NEXT: [[DEF1:%[0-9]+]]:_(<64 x s8>) = IMPLICIT_DEF67 ; AVX512F-NEXT: [[UV:%[0-9]+]]:_(<32 x s8>), [[UV1:%[0-9]+]]:_(<32 x s8>) = G_UNMERGE_VALUES [[DEF]](<64 x s8>)68 ; AVX512F-NEXT: [[UV2:%[0-9]+]]:_(<32 x s8>), [[UV3:%[0-9]+]]:_(<32 x s8>) = G_UNMERGE_VALUES [[DEF1]](<64 x s8>)69 ; AVX512F-NEXT: [[ADD:%[0-9]+]]:_(<32 x s8>) = G_ADD [[UV]], [[UV2]]70 ; AVX512F-NEXT: [[ADD1:%[0-9]+]]:_(<32 x s8>) = G_ADD [[UV1]], [[UV3]]71 ; AVX512F-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<64 x s8>) = G_CONCAT_VECTORS [[ADD]](<32 x s8>), [[ADD1]](<32 x s8>)72 ; AVX512F-NEXT: $zmm0 = COPY [[CONCAT_VECTORS]](<64 x s8>)73 ; AVX512F-NEXT: RET 074 ;75 ; AVX512BW-LABEL: name: test_add_v64i876 ; AVX512BW: liveins: $zmm0, $zmm177 ; AVX512BW-NEXT: {{ $}}78 ; AVX512BW-NEXT: [[DEF:%[0-9]+]]:_(<64 x s8>) = IMPLICIT_DEF79 ; AVX512BW-NEXT: [[DEF1:%[0-9]+]]:_(<64 x s8>) = IMPLICIT_DEF80 ; AVX512BW-NEXT: [[ADD:%[0-9]+]]:_(<64 x s8>) = G_ADD [[DEF]], [[DEF1]]81 ; AVX512BW-NEXT: $zmm0 = COPY [[ADD]](<64 x s8>)82 ; AVX512BW-NEXT: RET 083 %0(<64 x s8>) = IMPLICIT_DEF84 %1(<64 x s8>) = IMPLICIT_DEF85 %2(<64 x s8>) = G_ADD %0, %186 $zmm0 = COPY %287 RET 088 89...90---91name: test_add_v32i1692alignment: 1693legalized: false94regBankSelected: false95registers:96 - { id: 0, class: _ }97 - { id: 1, class: _ }98 - { id: 2, class: _ }99body: |100 bb.1 (%ir-block.0):101 liveins: $zmm0, $zmm1102 103 ; AVX1-LABEL: name: test_add_v32i16104 ; AVX1: liveins: $zmm0, $zmm1105 ; AVX1-NEXT: {{ $}}106 ; AVX1-NEXT: [[DEF:%[0-9]+]]:_(<32 x s16>) = IMPLICIT_DEF107 ; AVX1-NEXT: [[DEF1:%[0-9]+]]:_(<32 x s16>) = IMPLICIT_DEF108 ; AVX1-NEXT: [[UV:%[0-9]+]]:_(<8 x s16>), [[UV1:%[0-9]+]]:_(<8 x s16>), [[UV2:%[0-9]+]]:_(<8 x s16>), [[UV3:%[0-9]+]]:_(<8 x s16>) = G_UNMERGE_VALUES [[DEF]](<32 x s16>)109 ; AVX1-NEXT: [[UV4:%[0-9]+]]:_(<8 x s16>), [[UV5:%[0-9]+]]:_(<8 x s16>), [[UV6:%[0-9]+]]:_(<8 x s16>), [[UV7:%[0-9]+]]:_(<8 x s16>) = G_UNMERGE_VALUES [[DEF1]](<32 x s16>)110 ; AVX1-NEXT: [[ADD:%[0-9]+]]:_(<8 x s16>) = G_ADD [[UV]], [[UV4]]111 ; AVX1-NEXT: [[ADD1:%[0-9]+]]:_(<8 x s16>) = G_ADD [[UV1]], [[UV5]]112 ; AVX1-NEXT: [[ADD2:%[0-9]+]]:_(<8 x s16>) = G_ADD [[UV2]], [[UV6]]113 ; AVX1-NEXT: [[ADD3:%[0-9]+]]:_(<8 x s16>) = G_ADD [[UV3]], [[UV7]]114 ; AVX1-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<32 x s16>) = G_CONCAT_VECTORS [[ADD]](<8 x s16>), [[ADD1]](<8 x s16>), [[ADD2]](<8 x s16>), [[ADD3]](<8 x s16>)115 ; AVX1-NEXT: $zmm0 = COPY [[CONCAT_VECTORS]](<32 x s16>)116 ; AVX1-NEXT: RET 0117 ;118 ; AVX512F-LABEL: name: test_add_v32i16119 ; AVX512F: liveins: $zmm0, $zmm1120 ; AVX512F-NEXT: {{ $}}121 ; AVX512F-NEXT: [[DEF:%[0-9]+]]:_(<32 x s16>) = IMPLICIT_DEF122 ; AVX512F-NEXT: [[DEF1:%[0-9]+]]:_(<32 x s16>) = IMPLICIT_DEF123 ; AVX512F-NEXT: [[UV:%[0-9]+]]:_(<16 x s16>), [[UV1:%[0-9]+]]:_(<16 x s16>) = G_UNMERGE_VALUES [[DEF]](<32 x s16>)124 ; AVX512F-NEXT: [[UV2:%[0-9]+]]:_(<16 x s16>), [[UV3:%[0-9]+]]:_(<16 x s16>) = G_UNMERGE_VALUES [[DEF1]](<32 x s16>)125 ; AVX512F-NEXT: [[ADD:%[0-9]+]]:_(<16 x s16>) = G_ADD [[UV]], [[UV2]]126 ; AVX512F-NEXT: [[ADD1:%[0-9]+]]:_(<16 x s16>) = G_ADD [[UV1]], [[UV3]]127 ; AVX512F-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<32 x s16>) = G_CONCAT_VECTORS [[ADD]](<16 x s16>), [[ADD1]](<16 x s16>)128 ; AVX512F-NEXT: $zmm0 = COPY [[CONCAT_VECTORS]](<32 x s16>)129 ; AVX512F-NEXT: RET 0130 ;131 ; AVX512BW-LABEL: name: test_add_v32i16132 ; AVX512BW: liveins: $zmm0, $zmm1133 ; AVX512BW-NEXT: {{ $}}134 ; AVX512BW-NEXT: [[DEF:%[0-9]+]]:_(<32 x s16>) = IMPLICIT_DEF135 ; AVX512BW-NEXT: [[DEF1:%[0-9]+]]:_(<32 x s16>) = IMPLICIT_DEF136 ; AVX512BW-NEXT: [[ADD:%[0-9]+]]:_(<32 x s16>) = G_ADD [[DEF]], [[DEF1]]137 ; AVX512BW-NEXT: $zmm0 = COPY [[ADD]](<32 x s16>)138 ; AVX512BW-NEXT: RET 0139 %0(<32 x s16>) = IMPLICIT_DEF140 %1(<32 x s16>) = IMPLICIT_DEF141 %2(<32 x s16>) = G_ADD %0, %1142 $zmm0 = COPY %2143 RET 0144 145...146---147name: test_add_v16i32148alignment: 16149legalized: false150regBankSelected: false151registers:152 - { id: 0, class: _ }153 - { id: 1, class: _ }154 - { id: 2, class: _ }155body: |156 bb.1 (%ir-block.0):157 liveins: $zmm0, $zmm1158 159 ; AVX1-LABEL: name: test_add_v16i32160 ; AVX1: liveins: $zmm0, $zmm1161 ; AVX1-NEXT: {{ $}}162 ; AVX1-NEXT: [[DEF:%[0-9]+]]:_(<16 x s32>) = IMPLICIT_DEF163 ; AVX1-NEXT: [[DEF1:%[0-9]+]]:_(<16 x s32>) = IMPLICIT_DEF164 ; AVX1-NEXT: [[UV:%[0-9]+]]:_(<4 x s32>), [[UV1:%[0-9]+]]:_(<4 x s32>), [[UV2:%[0-9]+]]:_(<4 x s32>), [[UV3:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[DEF]](<16 x s32>)165 ; AVX1-NEXT: [[UV4:%[0-9]+]]:_(<4 x s32>), [[UV5:%[0-9]+]]:_(<4 x s32>), [[UV6:%[0-9]+]]:_(<4 x s32>), [[UV7:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[DEF1]](<16 x s32>)166 ; AVX1-NEXT: [[ADD:%[0-9]+]]:_(<4 x s32>) = G_ADD [[UV]], [[UV4]]167 ; AVX1-NEXT: [[ADD1:%[0-9]+]]:_(<4 x s32>) = G_ADD [[UV1]], [[UV5]]168 ; AVX1-NEXT: [[ADD2:%[0-9]+]]:_(<4 x s32>) = G_ADD [[UV2]], [[UV6]]169 ; AVX1-NEXT: [[ADD3:%[0-9]+]]:_(<4 x s32>) = G_ADD [[UV3]], [[UV7]]170 ; AVX1-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<16 x s32>) = G_CONCAT_VECTORS [[ADD]](<4 x s32>), [[ADD1]](<4 x s32>), [[ADD2]](<4 x s32>), [[ADD3]](<4 x s32>)171 ; AVX1-NEXT: $zmm0 = COPY [[CONCAT_VECTORS]](<16 x s32>)172 ; AVX1-NEXT: RET 0173 ;174 ; AVX512F-LABEL: name: test_add_v16i32175 ; AVX512F: liveins: $zmm0, $zmm1176 ; AVX512F-NEXT: {{ $}}177 ; AVX512F-NEXT: [[DEF:%[0-9]+]]:_(<16 x s32>) = IMPLICIT_DEF178 ; AVX512F-NEXT: [[DEF1:%[0-9]+]]:_(<16 x s32>) = IMPLICIT_DEF179 ; AVX512F-NEXT: [[ADD:%[0-9]+]]:_(<16 x s32>) = G_ADD [[DEF]], [[DEF1]]180 ; AVX512F-NEXT: $zmm0 = COPY [[ADD]](<16 x s32>)181 ; AVX512F-NEXT: RET 0182 ;183 ; AVX512BW-LABEL: name: test_add_v16i32184 ; AVX512BW: liveins: $zmm0, $zmm1185 ; AVX512BW-NEXT: {{ $}}186 ; AVX512BW-NEXT: [[DEF:%[0-9]+]]:_(<16 x s32>) = IMPLICIT_DEF187 ; AVX512BW-NEXT: [[DEF1:%[0-9]+]]:_(<16 x s32>) = IMPLICIT_DEF188 ; AVX512BW-NEXT: [[ADD:%[0-9]+]]:_(<16 x s32>) = G_ADD [[DEF]], [[DEF1]]189 ; AVX512BW-NEXT: $zmm0 = COPY [[ADD]](<16 x s32>)190 ; AVX512BW-NEXT: RET 0191 %0(<16 x s32>) = IMPLICIT_DEF192 %1(<16 x s32>) = IMPLICIT_DEF193 %2(<16 x s32>) = G_ADD %0, %1194 $zmm0 = COPY %2195 RET 0196 197...198---199name: test_add_v8i64200alignment: 16201legalized: false202regBankSelected: false203registers:204 - { id: 0, class: _ }205 - { id: 1, class: _ }206 - { id: 2, class: _ }207body: |208 bb.1 (%ir-block.0):209 liveins: $zmm0, $zmm1210 211 ; AVX1-LABEL: name: test_add_v8i64212 ; AVX1: liveins: $zmm0, $zmm1213 ; AVX1-NEXT: {{ $}}214 ; AVX1-NEXT: [[DEF:%[0-9]+]]:_(<8 x s64>) = IMPLICIT_DEF215 ; AVX1-NEXT: [[DEF1:%[0-9]+]]:_(<8 x s64>) = IMPLICIT_DEF216 ; AVX1-NEXT: [[UV:%[0-9]+]]:_(<2 x s64>), [[UV1:%[0-9]+]]:_(<2 x s64>), [[UV2:%[0-9]+]]:_(<2 x s64>), [[UV3:%[0-9]+]]:_(<2 x s64>) = G_UNMERGE_VALUES [[DEF]](<8 x s64>)217 ; AVX1-NEXT: [[UV4:%[0-9]+]]:_(<2 x s64>), [[UV5:%[0-9]+]]:_(<2 x s64>), [[UV6:%[0-9]+]]:_(<2 x s64>), [[UV7:%[0-9]+]]:_(<2 x s64>) = G_UNMERGE_VALUES [[DEF1]](<8 x s64>)218 ; AVX1-NEXT: [[ADD:%[0-9]+]]:_(<2 x s64>) = G_ADD [[UV]], [[UV4]]219 ; AVX1-NEXT: [[ADD1:%[0-9]+]]:_(<2 x s64>) = G_ADD [[UV1]], [[UV5]]220 ; AVX1-NEXT: [[ADD2:%[0-9]+]]:_(<2 x s64>) = G_ADD [[UV2]], [[UV6]]221 ; AVX1-NEXT: [[ADD3:%[0-9]+]]:_(<2 x s64>) = G_ADD [[UV3]], [[UV7]]222 ; AVX1-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s64>) = G_CONCAT_VECTORS [[ADD]](<2 x s64>), [[ADD1]](<2 x s64>), [[ADD2]](<2 x s64>), [[ADD3]](<2 x s64>)223 ; AVX1-NEXT: $zmm0 = COPY [[CONCAT_VECTORS]](<8 x s64>)224 ; AVX1-NEXT: RET 0225 ;226 ; AVX512F-LABEL: name: test_add_v8i64227 ; AVX512F: liveins: $zmm0, $zmm1228 ; AVX512F-NEXT: {{ $}}229 ; AVX512F-NEXT: [[DEF:%[0-9]+]]:_(<8 x s64>) = IMPLICIT_DEF230 ; AVX512F-NEXT: [[DEF1:%[0-9]+]]:_(<8 x s64>) = IMPLICIT_DEF231 ; AVX512F-NEXT: [[ADD:%[0-9]+]]:_(<8 x s64>) = G_ADD [[DEF]], [[DEF1]]232 ; AVX512F-NEXT: $zmm0 = COPY [[ADD]](<8 x s64>)233 ; AVX512F-NEXT: RET 0234 ;235 ; AVX512BW-LABEL: name: test_add_v8i64236 ; AVX512BW: liveins: $zmm0, $zmm1237 ; AVX512BW-NEXT: {{ $}}238 ; AVX512BW-NEXT: [[DEF:%[0-9]+]]:_(<8 x s64>) = IMPLICIT_DEF239 ; AVX512BW-NEXT: [[DEF1:%[0-9]+]]:_(<8 x s64>) = IMPLICIT_DEF240 ; AVX512BW-NEXT: [[ADD:%[0-9]+]]:_(<8 x s64>) = G_ADD [[DEF]], [[DEF1]]241 ; AVX512BW-NEXT: $zmm0 = COPY [[ADD]](<8 x s64>)242 ; AVX512BW-NEXT: RET 0243 %0(<8 x s64>) = IMPLICIT_DEF244 %1(<8 x s64>) = IMPLICIT_DEF245 %2(<8 x s64>) = G_ADD %0, %1246 $zmm0 = COPY %2247 RET 0248 249...250---251name: test_add_v64i8_2252alignment: 16253legalized: false254regBankSelected: false255registers:256 - { id: 0, class: _ }257 - { id: 1, class: _ }258 - { id: 2, class: _ }259 - { id: 3, class: _ }260 - { id: 4, class: _ }261 - { id: 5, class: _ }262 - { id: 6, class: _ }263 - { id: 7, class: _ }264 - { id: 8, class: _ }265#266#267body: |268 bb.1 (%ir-block.0):269 liveins: $ymm0, $ymm1, $ymm2, $ymm3270 ; AVX1-LABEL: name: test_add_v64i8_2271 ; AVX1: liveins: $ymm0, $ymm1, $ymm2, $ymm3272 ; AVX1-NEXT: {{ $}}273 ; AVX1-NEXT: [[COPY:%[0-9]+]]:_(<32 x s8>) = COPY $ymm0274 ; AVX1-NEXT: [[COPY1:%[0-9]+]]:_(<32 x s8>) = COPY $ymm1275 ; AVX1-NEXT: [[COPY2:%[0-9]+]]:_(<32 x s8>) = COPY $ymm2276 ; AVX1-NEXT: [[COPY3:%[0-9]+]]:_(<32 x s8>) = COPY $ymm3277 ; AVX1-NEXT: [[UV:%[0-9]+]]:_(<16 x s8>), [[UV1:%[0-9]+]]:_(<16 x s8>) = G_UNMERGE_VALUES [[COPY]](<32 x s8>)278 ; AVX1-NEXT: [[UV2:%[0-9]+]]:_(<16 x s8>), [[UV3:%[0-9]+]]:_(<16 x s8>) = G_UNMERGE_VALUES [[COPY1]](<32 x s8>)279 ; AVX1-NEXT: [[UV4:%[0-9]+]]:_(<16 x s8>), [[UV5:%[0-9]+]]:_(<16 x s8>) = G_UNMERGE_VALUES [[COPY2]](<32 x s8>)280 ; AVX1-NEXT: [[UV6:%[0-9]+]]:_(<16 x s8>), [[UV7:%[0-9]+]]:_(<16 x s8>) = G_UNMERGE_VALUES [[COPY3]](<32 x s8>)281 ; AVX1-NEXT: [[ADD:%[0-9]+]]:_(<16 x s8>) = G_ADD [[UV]], [[UV4]]282 ; AVX1-NEXT: [[ADD1:%[0-9]+]]:_(<16 x s8>) = G_ADD [[UV1]], [[UV5]]283 ; AVX1-NEXT: [[ADD2:%[0-9]+]]:_(<16 x s8>) = G_ADD [[UV2]], [[UV6]]284 ; AVX1-NEXT: [[ADD3:%[0-9]+]]:_(<16 x s8>) = G_ADD [[UV3]], [[UV7]]285 ; AVX1-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<32 x s8>) = G_CONCAT_VECTORS [[ADD]](<16 x s8>), [[ADD1]](<16 x s8>)286 ; AVX1-NEXT: [[CONCAT_VECTORS1:%[0-9]+]]:_(<32 x s8>) = G_CONCAT_VECTORS [[ADD2]](<16 x s8>), [[ADD3]](<16 x s8>)287 ; AVX1-NEXT: $ymm0 = COPY [[CONCAT_VECTORS]](<32 x s8>)288 ; AVX1-NEXT: $ymm1 = COPY [[CONCAT_VECTORS1]](<32 x s8>)289 ; AVX1-NEXT: RET 0, implicit $ymm0, implicit $ymm1290 ;291 ; AVX512F-LABEL: name: test_add_v64i8_2292 ; AVX512F: liveins: $ymm0, $ymm1, $ymm2, $ymm3293 ; AVX512F-NEXT: {{ $}}294 ; AVX512F-NEXT: [[COPY:%[0-9]+]]:_(<32 x s8>) = COPY $ymm0295 ; AVX512F-NEXT: [[COPY1:%[0-9]+]]:_(<32 x s8>) = COPY $ymm1296 ; AVX512F-NEXT: [[COPY2:%[0-9]+]]:_(<32 x s8>) = COPY $ymm2297 ; AVX512F-NEXT: [[COPY3:%[0-9]+]]:_(<32 x s8>) = COPY $ymm3298 ; AVX512F-NEXT: [[ADD:%[0-9]+]]:_(<32 x s8>) = G_ADD [[COPY]], [[COPY2]]299 ; AVX512F-NEXT: [[ADD1:%[0-9]+]]:_(<32 x s8>) = G_ADD [[COPY1]], [[COPY3]]300 ; AVX512F-NEXT: $ymm0 = COPY [[ADD]](<32 x s8>)301 ; AVX512F-NEXT: $ymm1 = COPY [[ADD1]](<32 x s8>)302 ; AVX512F-NEXT: RET 0, implicit $ymm0, implicit $ymm1303 ;304 ; AVX512BW-LABEL: name: test_add_v64i8_2305 ; AVX512BW: liveins: $ymm0, $ymm1, $ymm2, $ymm3306 ; AVX512BW-NEXT: {{ $}}307 ; AVX512BW-NEXT: [[COPY:%[0-9]+]]:_(<32 x s8>) = COPY $ymm0308 ; AVX512BW-NEXT: [[COPY1:%[0-9]+]]:_(<32 x s8>) = COPY $ymm1309 ; AVX512BW-NEXT: [[COPY2:%[0-9]+]]:_(<32 x s8>) = COPY $ymm2310 ; AVX512BW-NEXT: [[COPY3:%[0-9]+]]:_(<32 x s8>) = COPY $ymm3311 ; AVX512BW-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<64 x s8>) = G_CONCAT_VECTORS [[COPY]](<32 x s8>), [[COPY1]](<32 x s8>)312 ; AVX512BW-NEXT: [[CONCAT_VECTORS1:%[0-9]+]]:_(<64 x s8>) = G_CONCAT_VECTORS [[COPY2]](<32 x s8>), [[COPY3]](<32 x s8>)313 ; AVX512BW-NEXT: [[ADD:%[0-9]+]]:_(<64 x s8>) = G_ADD [[CONCAT_VECTORS]], [[CONCAT_VECTORS1]]314 ; AVX512BW-NEXT: [[UV:%[0-9]+]]:_(<32 x s8>), [[UV1:%[0-9]+]]:_(<32 x s8>) = G_UNMERGE_VALUES [[ADD]](<64 x s8>)315 ; AVX512BW-NEXT: $ymm0 = COPY [[UV]](<32 x s8>)316 ; AVX512BW-NEXT: $ymm1 = COPY [[UV1]](<32 x s8>)317 ; AVX512BW-NEXT: RET 0, implicit $ymm0, implicit $ymm1318 %2(<32 x s8>) = COPY $ymm0319 %3(<32 x s8>) = COPY $ymm1320 %4(<32 x s8>) = COPY $ymm2321 %5(<32 x s8>) = COPY $ymm3322 %0(<64 x s8>) = G_CONCAT_VECTORS %2(<32 x s8>), %3(<32 x s8>)323 %1(<64 x s8>) = G_CONCAT_VECTORS %4(<32 x s8>), %5(<32 x s8>)324 %6(<64 x s8>) = G_ADD %0, %1325 %7(<32 x s8>), %8(<32 x s8>) = G_UNMERGE_VALUES %6(<64 x s8>)326 $ymm0 = COPY %7(<32 x s8>)327 $ymm1 = COPY %8(<32 x s8>)328 RET 0, implicit $ymm0, implicit $ymm1329 330...331