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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -O0 -mtriple=x86_64-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=CHECK,X643# RUN: llc -O0 -mtriple=i386-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=CHECK,X864 5--- |6 define void @test_mul_i1() { ret void }7 8 define i8 @test_mul_i8(i8 %arg1, i8 %arg2) {9 %ret = mul i8 %arg1, %arg210 ret i8 %ret11 }12 13 define i16 @test_mul_i16(i16 %arg1, i16 %arg2) {14 %ret = mul i16 %arg1, %arg215 ret i16 %ret16 }17 18 define i27 @test_mul_i27(i27 %arg1, i27 %arg2) {19 %ret = mul i27 %arg1, %arg220 ret i27 %ret21 }22 23 define i32 @test_mul_i32(i32 %arg1, i32 %arg2) {24 %ret = mul i32 %arg1, %arg225 ret i32 %ret26 }27 28 define i42 @test_mul_i42(i42 %arg1, i42 %arg2) {29 %ret = mul i42 %arg1, %arg230 ret i42 %ret31 }32 33 define i64 @test_mul_i64(i64 %arg1, i64 %arg2) {34 %ret = mul i64 %arg1, %arg235 ret i64 %ret36 }37...38---39name: test_mul_i140alignment: 1641legalized: false42regBankSelected: false43registers:44 - { id: 0, class: _, preferred-register: '' }45 - { id: 1, class: _, preferred-register: '' }46 - { id: 2, class: _, preferred-register: '' }47body: |48 bb.1 (%ir-block.0):49 50 ; CHECK-LABEL: name: test_mul_i151 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edx52 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)53 ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)54 ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s8) = G_MUL [[TRUNC]], [[TRUNC1]]55 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF56 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 157 ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s8) = G_AND [[MUL]], [[C]]58 ; CHECK-NEXT: G_STORE [[AND]](s8), [[DEF]](p0) :: (store (s8))59 ; CHECK-NEXT: RET 060 %0(s32) = COPY $edx61 %1(s1) = G_TRUNC %0(s32)62 %2(s1) = G_MUL %1, %163 %3:_(p0) = G_IMPLICIT_DEF64 G_STORE %2, %3 :: (store (s1))65 RET 066...67---68name: test_mul_i869alignment: 1670legalized: false71regBankSelected: false72registers:73 - { id: 0, class: _ }74 - { id: 1, class: _ }75 - { id: 2, class: _ }76body: |77 bb.1 (%ir-block.0):78 liveins: $edi, $esi79 80 ; CHECK-LABEL: name: test_mul_i881 ; CHECK: liveins: $edi, $esi82 ; CHECK-NEXT: {{ $}}83 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s8) = COPY $dl84 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s8) = COPY $sil85 ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s8) = G_MUL [[COPY]], [[COPY1]]86 ; CHECK-NEXT: $al = COPY [[MUL]](s8)87 ; CHECK-NEXT: RET 0, implicit $al88 %0(s8) = COPY $dl89 %1(s8) = COPY $sil90 %2(s8) = G_MUL %0, %191 $al = COPY %2(s8)92 RET 0, implicit $al93...94---95name: test_mul_i1696alignment: 1697legalized: false98regBankSelected: false99registers:100 - { id: 0, class: _ }101 - { id: 1, class: _ }102 - { id: 2, class: _ }103body: |104 bb.1 (%ir-block.0):105 liveins: $edi, $esi106 107 ; CHECK-LABEL: name: test_mul_i16108 ; CHECK: liveins: $edi, $esi109 ; CHECK-NEXT: {{ $}}110 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $di111 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s16) = COPY $si112 ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s16) = G_MUL [[COPY]], [[COPY1]]113 ; CHECK-NEXT: $ax = COPY [[MUL]](s16)114 ; CHECK-NEXT: RET 0, implicit $ax115 %0(s16) = COPY $di116 %1(s16) = COPY $si117 %2(s16) = G_MUL %0, %1118 $ax = COPY %2(s16)119 RET 0, implicit $ax120...121---122name: test_mul_i27123alignment: 16124legalized: false125regBankSelected: false126registers:127 - { id: 0, class: _ }128 - { id: 1, class: _ }129 - { id: 2, class: _ }130body: |131 bb.1 (%ir-block.0):132 133 ;134 ;135 ; CHECK-LABEL: name: test_mul_i27136 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edx137 ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY]], [[COPY]]138 ; CHECK-NEXT: $eax = COPY [[MUL]](s32)139 ; CHECK-NEXT: RET 0140 %0(s32) = COPY $edx141 %1(s27) = G_TRUNC %0(s32)142 %2(s27) = G_MUL %1, %1143 %3:_(s32) = G_ANYEXT %2144 $eax = COPY %3145 RET 0146...147---148 149name: test_mul_i32150alignment: 16151legalized: false152regBankSelected: false153registers:154 - { id: 0, class: _ }155 - { id: 1, class: _ }156 - { id: 2, class: _ }157body: |158 bb.1 (%ir-block.0):159 liveins: $edi, $esi160 161 ; CHECK-LABEL: name: test_mul_i32162 ; CHECK: liveins: $edi, $esi163 ; CHECK-NEXT: {{ $}}164 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $edi165 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $esi166 ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY]], [[COPY1]]167 ; CHECK-NEXT: $eax = COPY [[MUL]](s32)168 ; CHECK-NEXT: RET 0, implicit $eax169 %0(s32) = COPY $edi170 %1(s32) = COPY $esi171 %2(s32) = G_MUL %0, %1172 $eax = COPY %2(s32)173 RET 0, implicit $eax174...175---176name: test_mul_i42177alignment: 16178legalized: false179regBankSelected: false180registers:181 - { id: 0, class: _ }182 - { id: 1, class: _ }183 - { id: 2, class: _ }184body: |185 bb.1 (%ir-block.0):186 liveins: $rdi, $rsi187 188 ; X64-LABEL: name: test_mul_i42189 ; X64: liveins: $rdi, $rsi190 ; X64-NEXT: {{ $}}191 ; X64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $rdx192 ; X64-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[COPY]], [[COPY]]193 ; X64-NEXT: $rax = COPY [[MUL]](s64)194 ; X64-NEXT: RET 0195 ; X86-LABEL: name: test_mul_i42196 ; X86: liveins: $rdi, $rsi197 ; X86-NEXT: {{ $}}198 ; X86-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $rdx199 ; X86-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)200 ; X86-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)201 ; X86-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[UV]], [[UV2]]202 ; X86-NEXT: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[UV1]], [[UV2]]203 ; X86-NEXT: [[MUL2:%[0-9]+]]:_(s32) = G_MUL [[UV]], [[UV3]]204 ; X86-NEXT: [[UMULH:%[0-9]+]]:_(s32) = G_UMULH [[UV]], [[UV2]]205 ; X86-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[MUL1]], [[MUL2]]206 ; X86-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ADD]], [[UMULH]]207 ; X86-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[MUL]](s32), [[ADD1]](s32)208 ; X86-NEXT: $rax = COPY [[MV]](s64)209 ; X86-NEXT: RET 0210 %0(s64) = COPY $rdx211 %1(s42) = G_TRUNC %0(s64)212 %2(s42) = G_MUL %1, %1213 %3:_(s64) = G_ANYEXT %2214 $rax = COPY %3215 RET 0216...217---218name: test_mul_i64219alignment: 16220legalized: false221regBankSelected: false222registers:223 - { id: 0, class: _ }224 - { id: 1, class: _ }225 - { id: 2, class: _ }226body: |227 bb.1 (%ir-block.0):228 liveins: $rdi, $rsi229 230 ; X64-LABEL: name: test_mul_i64231 ; X64: liveins: $rdi, $rsi232 ; X64-NEXT: {{ $}}233 ; X64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $rdi234 ; X64-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $rsi235 ; X64-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[COPY]], [[COPY1]]236 ; X64-NEXT: $rax = COPY [[MUL]](s64)237 ; X64-NEXT: RET 0, implicit $rax238 ; X86-LABEL: name: test_mul_i64239 ; X86: liveins: $rdi, $rsi240 ; X86-NEXT: {{ $}}241 ; X86-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $rdi242 ; X86-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $rsi243 ; X86-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)244 ; X86-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s64)245 ; X86-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[UV]], [[UV2]]246 ; X86-NEXT: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[UV1]], [[UV2]]247 ; X86-NEXT: [[MUL2:%[0-9]+]]:_(s32) = G_MUL [[UV]], [[UV3]]248 ; X86-NEXT: [[UMULH:%[0-9]+]]:_(s32) = G_UMULH [[UV]], [[UV2]]249 ; X86-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[MUL1]], [[MUL2]]250 ; X86-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ADD]], [[UMULH]]251 ; X86-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[MUL]](s32), [[ADD1]](s32)252 ; X86-NEXT: $rax = COPY [[MV]](s64)253 ; X86-NEXT: RET 0, implicit $rax254 %0(s64) = COPY $rdi255 %1(s64) = COPY $rsi256 %2(s64) = G_MUL %0, %1257 $rax = COPY %2(s64)258 RET 0, implicit $rax259...260