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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+sse2 -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=SSE3# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=AVX4# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx2 -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=AVX5 6--- |7 define void @test_or_v32i8() {8 %ret = or <32 x i8> undef, undef9 ret void10 }11 12 define void @test_or_v16i16() {13 %ret = or <16 x i16> undef, undef14 ret void15 }16 17 define void @test_or_v8i32() {18 %ret = or <8 x i32> undef, undef19 ret void20 }21 22 define void @test_or_v4i64() {23 %ret = or <4 x i64> undef, undef24 ret void25 }26...27---28name: test_or_v32i829alignment: 1630legalized: false31regBankSelected: false32registers:33 - { id: 0, class: _ }34 - { id: 1, class: _ }35 - { id: 2, class: _ }36body: |37 bb.1 (%ir-block.0):38 liveins: $ymm0, $ymm139 40 ; SSE-LABEL: name: test_or_v32i841 ; SSE: liveins: $ymm0, $ymm142 ; SSE-NEXT: {{ $}}43 ; SSE-NEXT: [[DEF:%[0-9]+]]:_(<32 x s8>) = IMPLICIT_DEF44 ; SSE-NEXT: [[DEF1:%[0-9]+]]:_(<32 x s8>) = IMPLICIT_DEF45 ; SSE-NEXT: [[UV:%[0-9]+]]:_(<16 x s8>), [[UV1:%[0-9]+]]:_(<16 x s8>) = G_UNMERGE_VALUES [[DEF]](<32 x s8>)46 ; SSE-NEXT: [[UV2:%[0-9]+]]:_(<16 x s8>), [[UV3:%[0-9]+]]:_(<16 x s8>) = G_UNMERGE_VALUES [[DEF1]](<32 x s8>)47 ; SSE-NEXT: [[OR:%[0-9]+]]:_(<16 x s8>) = G_OR [[UV]], [[UV2]]48 ; SSE-NEXT: [[OR1:%[0-9]+]]:_(<16 x s8>) = G_OR [[UV1]], [[UV3]]49 ; SSE-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<32 x s8>) = G_CONCAT_VECTORS [[OR]](<16 x s8>), [[OR1]](<16 x s8>)50 ; SSE-NEXT: $ymm0 = COPY [[CONCAT_VECTORS]](<32 x s8>)51 ; SSE-NEXT: RET 052 ; AVX-LABEL: name: test_or_v32i853 ; AVX: liveins: $ymm0, $ymm154 ; AVX-NEXT: {{ $}}55 ; AVX-NEXT: [[DEF:%[0-9]+]]:_(<32 x s8>) = IMPLICIT_DEF56 ; AVX-NEXT: [[DEF1:%[0-9]+]]:_(<32 x s8>) = IMPLICIT_DEF57 ; AVX-NEXT: [[OR:%[0-9]+]]:_(<32 x s8>) = G_OR [[DEF]], [[DEF1]]58 ; AVX-NEXT: $ymm0 = COPY [[OR]](<32 x s8>)59 ; AVX-NEXT: RET 060 %0(<32 x s8>) = IMPLICIT_DEF61 %1(<32 x s8>) = IMPLICIT_DEF62 %2(<32 x s8>) = G_OR %0, %163 $ymm0 = COPY %264 RET 065...66---67name: test_or_v16i1668alignment: 1669legalized: false70regBankSelected: false71registers:72 - { id: 0, class: _ }73 - { id: 1, class: _ }74 - { id: 2, class: _ }75body: |76 bb.1 (%ir-block.0):77 liveins: $ymm0, $ymm178 79 ; SSE-LABEL: name: test_or_v16i1680 ; SSE: liveins: $ymm0, $ymm181 ; SSE-NEXT: {{ $}}82 ; SSE-NEXT: [[DEF:%[0-9]+]]:_(<16 x s16>) = IMPLICIT_DEF83 ; SSE-NEXT: [[DEF1:%[0-9]+]]:_(<16 x s16>) = IMPLICIT_DEF84 ; SSE-NEXT: [[UV:%[0-9]+]]:_(<8 x s16>), [[UV1:%[0-9]+]]:_(<8 x s16>) = G_UNMERGE_VALUES [[DEF]](<16 x s16>)85 ; SSE-NEXT: [[UV2:%[0-9]+]]:_(<8 x s16>), [[UV3:%[0-9]+]]:_(<8 x s16>) = G_UNMERGE_VALUES [[DEF1]](<16 x s16>)86 ; SSE-NEXT: [[OR:%[0-9]+]]:_(<8 x s16>) = G_OR [[UV]], [[UV2]]87 ; SSE-NEXT: [[OR1:%[0-9]+]]:_(<8 x s16>) = G_OR [[UV1]], [[UV3]]88 ; SSE-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<16 x s16>) = G_CONCAT_VECTORS [[OR]](<8 x s16>), [[OR1]](<8 x s16>)89 ; SSE-NEXT: $ymm0 = COPY [[CONCAT_VECTORS]](<16 x s16>)90 ; SSE-NEXT: RET 091 ; AVX-LABEL: name: test_or_v16i1692 ; AVX: liveins: $ymm0, $ymm193 ; AVX-NEXT: {{ $}}94 ; AVX-NEXT: [[DEF:%[0-9]+]]:_(<16 x s16>) = IMPLICIT_DEF95 ; AVX-NEXT: [[DEF1:%[0-9]+]]:_(<16 x s16>) = IMPLICIT_DEF96 ; AVX-NEXT: [[OR:%[0-9]+]]:_(<16 x s16>) = G_OR [[DEF]], [[DEF1]]97 ; AVX-NEXT: $ymm0 = COPY [[OR]](<16 x s16>)98 ; AVX-NEXT: RET 099 %0(<16 x s16>) = IMPLICIT_DEF100 %1(<16 x s16>) = IMPLICIT_DEF101 %2(<16 x s16>) = G_OR %0, %1102 $ymm0 = COPY %2103 RET 0104...105---106name: test_or_v8i32107alignment: 16108legalized: false109regBankSelected: false110registers:111 - { id: 0, class: _ }112 - { id: 1, class: _ }113 - { id: 2, class: _ }114body: |115 bb.1 (%ir-block.0):116 liveins: $ymm0, $ymm1117 118 ; SSE-LABEL: name: test_or_v8i32119 ; SSE: liveins: $ymm0, $ymm1120 ; SSE-NEXT: {{ $}}121 ; SSE-NEXT: [[DEF:%[0-9]+]]:_(<8 x s32>) = IMPLICIT_DEF122 ; SSE-NEXT: [[DEF1:%[0-9]+]]:_(<8 x s32>) = IMPLICIT_DEF123 ; SSE-NEXT: [[UV:%[0-9]+]]:_(<4 x s32>), [[UV1:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[DEF]](<8 x s32>)124 ; SSE-NEXT: [[UV2:%[0-9]+]]:_(<4 x s32>), [[UV3:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[DEF1]](<8 x s32>)125 ; SSE-NEXT: [[OR:%[0-9]+]]:_(<4 x s32>) = G_OR [[UV]], [[UV2]]126 ; SSE-NEXT: [[OR1:%[0-9]+]]:_(<4 x s32>) = G_OR [[UV1]], [[UV3]]127 ; SSE-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s32>) = G_CONCAT_VECTORS [[OR]](<4 x s32>), [[OR1]](<4 x s32>)128 ; SSE-NEXT: $ymm0 = COPY [[CONCAT_VECTORS]](<8 x s32>)129 ; SSE-NEXT: RET 0130 ; AVX-LABEL: name: test_or_v8i32131 ; AVX: liveins: $ymm0, $ymm1132 ; AVX-NEXT: {{ $}}133 ; AVX-NEXT: [[DEF:%[0-9]+]]:_(<8 x s32>) = IMPLICIT_DEF134 ; AVX-NEXT: [[DEF1:%[0-9]+]]:_(<8 x s32>) = IMPLICIT_DEF135 ; AVX-NEXT: [[OR:%[0-9]+]]:_(<8 x s32>) = G_OR [[DEF]], [[DEF1]]136 ; AVX-NEXT: $ymm0 = COPY [[OR]](<8 x s32>)137 ; AVX-NEXT: RET 0138 %0(<8 x s32>) = IMPLICIT_DEF139 %1(<8 x s32>) = IMPLICIT_DEF140 %2(<8 x s32>) = G_OR %0, %1141 $ymm0 = COPY %2142 RET 0143...144---145name: test_or_v4i64146alignment: 16147legalized: false148regBankSelected: false149registers:150 - { id: 0, class: _ }151 - { id: 1, class: _ }152 - { id: 2, class: _ }153body: |154 bb.1 (%ir-block.0):155 liveins: $ymm0, $ymm1156 157 ; SSE-LABEL: name: test_or_v4i64158 ; SSE: liveins: $ymm0, $ymm1159 ; SSE-NEXT: {{ $}}160 ; SSE-NEXT: [[DEF:%[0-9]+]]:_(<4 x s64>) = IMPLICIT_DEF161 ; SSE-NEXT: [[DEF1:%[0-9]+]]:_(<4 x s64>) = IMPLICIT_DEF162 ; SSE-NEXT: [[UV:%[0-9]+]]:_(<2 x s64>), [[UV1:%[0-9]+]]:_(<2 x s64>) = G_UNMERGE_VALUES [[DEF]](<4 x s64>)163 ; SSE-NEXT: [[UV2:%[0-9]+]]:_(<2 x s64>), [[UV3:%[0-9]+]]:_(<2 x s64>) = G_UNMERGE_VALUES [[DEF1]](<4 x s64>)164 ; SSE-NEXT: [[OR:%[0-9]+]]:_(<2 x s64>) = G_OR [[UV]], [[UV2]]165 ; SSE-NEXT: [[OR1:%[0-9]+]]:_(<2 x s64>) = G_OR [[UV1]], [[UV3]]166 ; SSE-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s64>) = G_CONCAT_VECTORS [[OR]](<2 x s64>), [[OR1]](<2 x s64>)167 ; SSE-NEXT: $ymm0 = COPY [[CONCAT_VECTORS]](<4 x s64>)168 ; SSE-NEXT: RET 0169 ; AVX-LABEL: name: test_or_v4i64170 ; AVX: liveins: $ymm0, $ymm1171 ; AVX-NEXT: {{ $}}172 ; AVX-NEXT: [[DEF:%[0-9]+]]:_(<4 x s64>) = IMPLICIT_DEF173 ; AVX-NEXT: [[DEF1:%[0-9]+]]:_(<4 x s64>) = IMPLICIT_DEF174 ; AVX-NEXT: [[OR:%[0-9]+]]:_(<4 x s64>) = G_OR [[DEF]], [[DEF1]]175 ; AVX-NEXT: $ymm0 = COPY [[OR]](<4 x s64>)176 ; AVX-NEXT: RET 0177 %0(<4 x s64>) = IMPLICIT_DEF178 %1(<4 x s64>) = IMPLICIT_DEF179 %2(<4 x s64>) = G_OR %0, %1180 $ymm0 = COPY %2181 RET 0182...183