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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=AVX3# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx2 -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=AVX4# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=AVX5125# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f,+avx512bw -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=AVX5126 7--- |8 define void @test_or_v64i8() {9 %ret = or <64 x i8> undef, undef10 ret void11 }12 13 define void @test_or_v32i16() {14 %ret = or <32 x i16> undef, undef15 ret void16 }17 18 define void @test_or_v16i32() {19 %ret = or <16 x i32> undef, undef20 ret void21 }22 23 define void @test_or_v8i64() {24 %ret = or <8 x i64> undef, undef25 ret void26 }27 28 define <64 x i8> @test_or_v64i8_2(<64 x i8> %arg1, <64 x i8> %arg2) #0 {29 %ret = or <64 x i8> %arg1, %arg230 ret <64 x i8> %ret31 }32...33---34name: test_or_v64i835alignment: 1636legalized: false37regBankSelected: false38registers:39 - { id: 0, class: _ }40 - { id: 1, class: _ }41 - { id: 2, class: _ }42body: |43 bb.1 (%ir-block.0):44 liveins: $zmm0, $zmm145 46 ; AVX-LABEL: name: test_or_v64i847 ; AVX: liveins: $zmm0, $zmm148 ; AVX-NEXT: {{ $}}49 ; AVX-NEXT: [[DEF:%[0-9]+]]:_(<64 x s8>) = IMPLICIT_DEF50 ; AVX-NEXT: [[DEF1:%[0-9]+]]:_(<64 x s8>) = IMPLICIT_DEF51 ; AVX-NEXT: [[UV:%[0-9]+]]:_(<32 x s8>), [[UV1:%[0-9]+]]:_(<32 x s8>) = G_UNMERGE_VALUES [[DEF]](<64 x s8>)52 ; AVX-NEXT: [[UV2:%[0-9]+]]:_(<32 x s8>), [[UV3:%[0-9]+]]:_(<32 x s8>) = G_UNMERGE_VALUES [[DEF1]](<64 x s8>)53 ; AVX-NEXT: [[OR:%[0-9]+]]:_(<32 x s8>) = G_OR [[UV]], [[UV2]]54 ; AVX-NEXT: [[OR1:%[0-9]+]]:_(<32 x s8>) = G_OR [[UV1]], [[UV3]]55 ; AVX-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<64 x s8>) = G_CONCAT_VECTORS [[OR]](<32 x s8>), [[OR1]](<32 x s8>)56 ; AVX-NEXT: $zmm0 = COPY [[CONCAT_VECTORS]](<64 x s8>)57 ; AVX-NEXT: RET 058 ; AVX512-LABEL: name: test_or_v64i859 ; AVX512: liveins: $zmm0, $zmm160 ; AVX512-NEXT: {{ $}}61 ; AVX512-NEXT: [[DEF:%[0-9]+]]:_(<64 x s8>) = IMPLICIT_DEF62 ; AVX512-NEXT: [[DEF1:%[0-9]+]]:_(<64 x s8>) = IMPLICIT_DEF63 ; AVX512-NEXT: [[OR:%[0-9]+]]:_(<64 x s8>) = G_OR [[DEF]], [[DEF1]]64 ; AVX512-NEXT: $zmm0 = COPY [[OR]](<64 x s8>)65 ; AVX512-NEXT: RET 066 %0(<64 x s8>) = IMPLICIT_DEF67 %1(<64 x s8>) = IMPLICIT_DEF68 %2(<64 x s8>) = G_OR %0, %169 $zmm0 = COPY %270 RET 071...72---73name: test_or_v32i1674alignment: 1675legalized: false76regBankSelected: false77registers:78 - { id: 0, class: _ }79 - { id: 1, class: _ }80 - { id: 2, class: _ }81body: |82 bb.1 (%ir-block.0):83 liveins: $zmm0, $zmm184 85 ; AVX-LABEL: name: test_or_v32i1686 ; AVX: liveins: $zmm0, $zmm187 ; AVX-NEXT: {{ $}}88 ; AVX-NEXT: [[DEF:%[0-9]+]]:_(<32 x s16>) = IMPLICIT_DEF89 ; AVX-NEXT: [[DEF1:%[0-9]+]]:_(<32 x s16>) = IMPLICIT_DEF90 ; AVX-NEXT: [[UV:%[0-9]+]]:_(<16 x s16>), [[UV1:%[0-9]+]]:_(<16 x s16>) = G_UNMERGE_VALUES [[DEF]](<32 x s16>)91 ; AVX-NEXT: [[UV2:%[0-9]+]]:_(<16 x s16>), [[UV3:%[0-9]+]]:_(<16 x s16>) = G_UNMERGE_VALUES [[DEF1]](<32 x s16>)92 ; AVX-NEXT: [[OR:%[0-9]+]]:_(<16 x s16>) = G_OR [[UV]], [[UV2]]93 ; AVX-NEXT: [[OR1:%[0-9]+]]:_(<16 x s16>) = G_OR [[UV1]], [[UV3]]94 ; AVX-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<32 x s16>) = G_CONCAT_VECTORS [[OR]](<16 x s16>), [[OR1]](<16 x s16>)95 ; AVX-NEXT: $zmm0 = COPY [[CONCAT_VECTORS]](<32 x s16>)96 ; AVX-NEXT: RET 097 ; AVX512-LABEL: name: test_or_v32i1698 ; AVX512: liveins: $zmm0, $zmm199 ; AVX512-NEXT: {{ $}}100 ; AVX512-NEXT: [[DEF:%[0-9]+]]:_(<32 x s16>) = IMPLICIT_DEF101 ; AVX512-NEXT: [[DEF1:%[0-9]+]]:_(<32 x s16>) = IMPLICIT_DEF102 ; AVX512-NEXT: [[OR:%[0-9]+]]:_(<32 x s16>) = G_OR [[DEF]], [[DEF1]]103 ; AVX512-NEXT: $zmm0 = COPY [[OR]](<32 x s16>)104 ; AVX512-NEXT: RET 0105 %0(<32 x s16>) = IMPLICIT_DEF106 %1(<32 x s16>) = IMPLICIT_DEF107 %2(<32 x s16>) = G_OR %0, %1108 $zmm0 = COPY %2109 RET 0110...111---112name: test_or_v16i32113alignment: 16114legalized: false115regBankSelected: false116registers:117 - { id: 0, class: _ }118 - { id: 1, class: _ }119 - { id: 2, class: _ }120body: |121 bb.1 (%ir-block.0):122 liveins: $zmm0, $zmm1123 124 ; AVX-LABEL: name: test_or_v16i32125 ; AVX: liveins: $zmm0, $zmm1126 ; AVX-NEXT: {{ $}}127 ; AVX-NEXT: [[DEF:%[0-9]+]]:_(<16 x s32>) = IMPLICIT_DEF128 ; AVX-NEXT: [[DEF1:%[0-9]+]]:_(<16 x s32>) = IMPLICIT_DEF129 ; AVX-NEXT: [[UV:%[0-9]+]]:_(<8 x s32>), [[UV1:%[0-9]+]]:_(<8 x s32>) = G_UNMERGE_VALUES [[DEF]](<16 x s32>)130 ; AVX-NEXT: [[UV2:%[0-9]+]]:_(<8 x s32>), [[UV3:%[0-9]+]]:_(<8 x s32>) = G_UNMERGE_VALUES [[DEF1]](<16 x s32>)131 ; AVX-NEXT: [[OR:%[0-9]+]]:_(<8 x s32>) = G_OR [[UV]], [[UV2]]132 ; AVX-NEXT: [[OR1:%[0-9]+]]:_(<8 x s32>) = G_OR [[UV1]], [[UV3]]133 ; AVX-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<16 x s32>) = G_CONCAT_VECTORS [[OR]](<8 x s32>), [[OR1]](<8 x s32>)134 ; AVX-NEXT: $zmm0 = COPY [[CONCAT_VECTORS]](<16 x s32>)135 ; AVX-NEXT: RET 0136 ; AVX512-LABEL: name: test_or_v16i32137 ; AVX512: liveins: $zmm0, $zmm1138 ; AVX512-NEXT: {{ $}}139 ; AVX512-NEXT: [[DEF:%[0-9]+]]:_(<16 x s32>) = IMPLICIT_DEF140 ; AVX512-NEXT: [[DEF1:%[0-9]+]]:_(<16 x s32>) = IMPLICIT_DEF141 ; AVX512-NEXT: [[OR:%[0-9]+]]:_(<16 x s32>) = G_OR [[DEF]], [[DEF1]]142 ; AVX512-NEXT: $zmm0 = COPY [[OR]](<16 x s32>)143 ; AVX512-NEXT: RET 0144 %0(<16 x s32>) = IMPLICIT_DEF145 %1(<16 x s32>) = IMPLICIT_DEF146 %2(<16 x s32>) = G_OR %0, %1147 $zmm0 = COPY %2148 RET 0149...150---151name: test_or_v8i64152alignment: 16153legalized: false154regBankSelected: false155registers:156 - { id: 0, class: _ }157 - { id: 1, class: _ }158 - { id: 2, class: _ }159body: |160 bb.1 (%ir-block.0):161 liveins: $zmm0, $zmm1162 163 ; AVX-LABEL: name: test_or_v8i64164 ; AVX: liveins: $zmm0, $zmm1165 ; AVX-NEXT: {{ $}}166 ; AVX-NEXT: [[DEF:%[0-9]+]]:_(<8 x s64>) = IMPLICIT_DEF167 ; AVX-NEXT: [[DEF1:%[0-9]+]]:_(<8 x s64>) = IMPLICIT_DEF168 ; AVX-NEXT: [[UV:%[0-9]+]]:_(<4 x s64>), [[UV1:%[0-9]+]]:_(<4 x s64>) = G_UNMERGE_VALUES [[DEF]](<8 x s64>)169 ; AVX-NEXT: [[UV2:%[0-9]+]]:_(<4 x s64>), [[UV3:%[0-9]+]]:_(<4 x s64>) = G_UNMERGE_VALUES [[DEF1]](<8 x s64>)170 ; AVX-NEXT: [[OR:%[0-9]+]]:_(<4 x s64>) = G_OR [[UV]], [[UV2]]171 ; AVX-NEXT: [[OR1:%[0-9]+]]:_(<4 x s64>) = G_OR [[UV1]], [[UV3]]172 ; AVX-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s64>) = G_CONCAT_VECTORS [[OR]](<4 x s64>), [[OR1]](<4 x s64>)173 ; AVX-NEXT: $zmm0 = COPY [[CONCAT_VECTORS]](<8 x s64>)174 ; AVX-NEXT: RET 0175 ; AVX512-LABEL: name: test_or_v8i64176 ; AVX512: liveins: $zmm0, $zmm1177 ; AVX512-NEXT: {{ $}}178 ; AVX512-NEXT: [[DEF:%[0-9]+]]:_(<8 x s64>) = IMPLICIT_DEF179 ; AVX512-NEXT: [[DEF1:%[0-9]+]]:_(<8 x s64>) = IMPLICIT_DEF180 ; AVX512-NEXT: [[OR:%[0-9]+]]:_(<8 x s64>) = G_OR [[DEF]], [[DEF1]]181 ; AVX512-NEXT: $zmm0 = COPY [[OR]](<8 x s64>)182 ; AVX512-NEXT: RET 0183 %0(<8 x s64>) = IMPLICIT_DEF184 %1(<8 x s64>) = IMPLICIT_DEF185 %2(<8 x s64>) = G_OR %0, %1186 $zmm0 = COPY %2187 RET 0188...189---190name: test_or_v64i8_2191alignment: 16192legalized: false193regBankSelected: false194registers:195 - { id: 0, class: _ }196 - { id: 1, class: _ }197 - { id: 2, class: _ }198 - { id: 3, class: _ }199 - { id: 4, class: _ }200 - { id: 5, class: _ }201 - { id: 6, class: _ }202 - { id: 7, class: _ }203 - { id: 8, class: _ }204#205#206body: |207 bb.1 (%ir-block.0):208 liveins: $ymm0, $ymm1, $ymm2, $ymm3209 ; AVX-LABEL: name: test_or_v64i8_2210 ; AVX: liveins: $ymm0, $ymm1, $ymm2, $ymm3211 ; AVX-NEXT: {{ $}}212 ; AVX-NEXT: [[COPY:%[0-9]+]]:_(<32 x s8>) = COPY $ymm0213 ; AVX-NEXT: [[COPY1:%[0-9]+]]:_(<32 x s8>) = COPY $ymm1214 ; AVX-NEXT: [[COPY2:%[0-9]+]]:_(<32 x s8>) = COPY $ymm2215 ; AVX-NEXT: [[COPY3:%[0-9]+]]:_(<32 x s8>) = COPY $ymm3216 ; AVX-NEXT: [[OR:%[0-9]+]]:_(<32 x s8>) = G_OR [[COPY]], [[COPY2]]217 ; AVX-NEXT: [[OR1:%[0-9]+]]:_(<32 x s8>) = G_OR [[COPY1]], [[COPY3]]218 ; AVX-NEXT: $ymm0 = COPY [[OR]](<32 x s8>)219 ; AVX-NEXT: $ymm1 = COPY [[OR1]](<32 x s8>)220 ; AVX-NEXT: RET 0, implicit $ymm0, implicit $ymm1221 ; AVX512-LABEL: name: test_or_v64i8_2222 ; AVX512: liveins: $ymm0, $ymm1, $ymm2, $ymm3223 ; AVX512-NEXT: {{ $}}224 ; AVX512-NEXT: [[COPY:%[0-9]+]]:_(<32 x s8>) = COPY $ymm0225 ; AVX512-NEXT: [[COPY1:%[0-9]+]]:_(<32 x s8>) = COPY $ymm1226 ; AVX512-NEXT: [[COPY2:%[0-9]+]]:_(<32 x s8>) = COPY $ymm2227 ; AVX512-NEXT: [[COPY3:%[0-9]+]]:_(<32 x s8>) = COPY $ymm3228 ; AVX512-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<64 x s8>) = G_CONCAT_VECTORS [[COPY]](<32 x s8>), [[COPY1]](<32 x s8>)229 ; AVX512-NEXT: [[CONCAT_VECTORS1:%[0-9]+]]:_(<64 x s8>) = G_CONCAT_VECTORS [[COPY2]](<32 x s8>), [[COPY3]](<32 x s8>)230 ; AVX512-NEXT: [[OR:%[0-9]+]]:_(<64 x s8>) = G_OR [[CONCAT_VECTORS]], [[CONCAT_VECTORS1]]231 ; AVX512-NEXT: [[UV:%[0-9]+]]:_(<32 x s8>), [[UV1:%[0-9]+]]:_(<32 x s8>) = G_UNMERGE_VALUES [[OR]](<64 x s8>)232 ; AVX512-NEXT: $ymm0 = COPY [[UV]](<32 x s8>)233 ; AVX512-NEXT: $ymm1 = COPY [[UV1]](<32 x s8>)234 ; AVX512-NEXT: RET 0, implicit $ymm0, implicit $ymm1235 %2(<32 x s8>) = COPY $ymm0236 %3(<32 x s8>) = COPY $ymm1237 %4(<32 x s8>) = COPY $ymm2238 %5(<32 x s8>) = COPY $ymm3239 %0(<64 x s8>) = G_CONCAT_VECTORS %2(<32 x s8>), %3(<32 x s8>)240 %1(<64 x s8>) = G_CONCAT_VECTORS %4(<32 x s8>), %5(<32 x s8>)241 %6(<64 x s8>) = G_OR %0, %1242 %7(<32 x s8>), %8(<32 x s8>) = G_UNMERGE_VALUES %6(<64 x s8>)243 $ymm0 = COPY %7(<32 x s8>)244 $ymm1 = COPY %8(<32 x s8>)245 RET 0, implicit $ymm0, implicit $ymm1246...247