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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+sse2 -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=SSE23# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=AVX14# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx2 -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=AVX25 6# TODO: add tests for additional configuration after the legalization supported7 8--- |9 define void @test_sub_v32i8() {10 %ret = sub <32 x i8> undef, undef11 ret void12 }13 14 define void @test_sub_v16i16() {15 %ret = sub <16 x i16> undef, undef16 ret void17 }18 19 define void @test_sub_v8i32() {20 %ret = sub <8 x i32> undef, undef21 ret void22 }23 24 define void @test_sub_v4i64() {25 %ret = sub <4 x i64> undef, undef26 ret void27 }28 29...30---31name: test_sub_v32i832alignment: 1633legalized: false34regBankSelected: false35registers:36 - { id: 0, class: _ }37 - { id: 1, class: _ }38 - { id: 2, class: _ }39body: |40 bb.1 (%ir-block.0):41 liveins: $ymm0, $ymm142 43 ; SSE2-LABEL: name: test_sub_v32i844 ; SSE2: liveins: $ymm0, $ymm145 ; SSE2-NEXT: {{ $}}46 ; SSE2-NEXT: [[DEF:%[0-9]+]]:_(<32 x s8>) = IMPLICIT_DEF47 ; SSE2-NEXT: [[DEF1:%[0-9]+]]:_(<32 x s8>) = IMPLICIT_DEF48 ; SSE2-NEXT: [[UV:%[0-9]+]]:_(<16 x s8>), [[UV1:%[0-9]+]]:_(<16 x s8>) = G_UNMERGE_VALUES [[DEF]](<32 x s8>)49 ; SSE2-NEXT: [[UV2:%[0-9]+]]:_(<16 x s8>), [[UV3:%[0-9]+]]:_(<16 x s8>) = G_UNMERGE_VALUES [[DEF1]](<32 x s8>)50 ; SSE2-NEXT: [[SUB:%[0-9]+]]:_(<16 x s8>) = G_SUB [[UV]], [[UV2]]51 ; SSE2-NEXT: [[SUB1:%[0-9]+]]:_(<16 x s8>) = G_SUB [[UV1]], [[UV3]]52 ; SSE2-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<32 x s8>) = G_CONCAT_VECTORS [[SUB]](<16 x s8>), [[SUB1]](<16 x s8>)53 ; SSE2-NEXT: $ymm0 = COPY [[CONCAT_VECTORS]](<32 x s8>)54 ; SSE2-NEXT: RET 055 ;56 ; AVX1-LABEL: name: test_sub_v32i857 ; AVX1: liveins: $ymm0, $ymm158 ; AVX1-NEXT: {{ $}}59 ; AVX1-NEXT: [[DEF:%[0-9]+]]:_(<32 x s8>) = IMPLICIT_DEF60 ; AVX1-NEXT: [[DEF1:%[0-9]+]]:_(<32 x s8>) = IMPLICIT_DEF61 ; AVX1-NEXT: [[UV:%[0-9]+]]:_(<16 x s8>), [[UV1:%[0-9]+]]:_(<16 x s8>) = G_UNMERGE_VALUES [[DEF]](<32 x s8>)62 ; AVX1-NEXT: [[UV2:%[0-9]+]]:_(<16 x s8>), [[UV3:%[0-9]+]]:_(<16 x s8>) = G_UNMERGE_VALUES [[DEF1]](<32 x s8>)63 ; AVX1-NEXT: [[SUB:%[0-9]+]]:_(<16 x s8>) = G_SUB [[UV]], [[UV2]]64 ; AVX1-NEXT: [[SUB1:%[0-9]+]]:_(<16 x s8>) = G_SUB [[UV1]], [[UV3]]65 ; AVX1-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<32 x s8>) = G_CONCAT_VECTORS [[SUB]](<16 x s8>), [[SUB1]](<16 x s8>)66 ; AVX1-NEXT: $ymm0 = COPY [[CONCAT_VECTORS]](<32 x s8>)67 ; AVX1-NEXT: RET 068 ;69 ; AVX2-LABEL: name: test_sub_v32i870 ; AVX2: liveins: $ymm0, $ymm171 ; AVX2-NEXT: {{ $}}72 ; AVX2-NEXT: [[DEF:%[0-9]+]]:_(<32 x s8>) = IMPLICIT_DEF73 ; AVX2-NEXT: [[DEF1:%[0-9]+]]:_(<32 x s8>) = IMPLICIT_DEF74 ; AVX2-NEXT: [[SUB:%[0-9]+]]:_(<32 x s8>) = G_SUB [[DEF]], [[DEF1]]75 ; AVX2-NEXT: $ymm0 = COPY [[SUB]](<32 x s8>)76 ; AVX2-NEXT: RET 077 %0(<32 x s8>) = IMPLICIT_DEF78 %1(<32 x s8>) = IMPLICIT_DEF79 %2(<32 x s8>) = G_SUB %0, %180 $ymm0 = COPY %281 RET 082 83...84---85name: test_sub_v16i1686alignment: 1687legalized: false88regBankSelected: false89registers:90 - { id: 0, class: _ }91 - { id: 1, class: _ }92 - { id: 2, class: _ }93body: |94 bb.1 (%ir-block.0):95 liveins: $ymm0, $ymm196 97 ; SSE2-LABEL: name: test_sub_v16i1698 ; SSE2: liveins: $ymm0, $ymm199 ; SSE2-NEXT: {{ $}}100 ; SSE2-NEXT: [[DEF:%[0-9]+]]:_(<16 x s16>) = IMPLICIT_DEF101 ; SSE2-NEXT: [[DEF1:%[0-9]+]]:_(<16 x s16>) = IMPLICIT_DEF102 ; SSE2-NEXT: [[UV:%[0-9]+]]:_(<8 x s16>), [[UV1:%[0-9]+]]:_(<8 x s16>) = G_UNMERGE_VALUES [[DEF]](<16 x s16>)103 ; SSE2-NEXT: [[UV2:%[0-9]+]]:_(<8 x s16>), [[UV3:%[0-9]+]]:_(<8 x s16>) = G_UNMERGE_VALUES [[DEF1]](<16 x s16>)104 ; SSE2-NEXT: [[SUB:%[0-9]+]]:_(<8 x s16>) = G_SUB [[UV]], [[UV2]]105 ; SSE2-NEXT: [[SUB1:%[0-9]+]]:_(<8 x s16>) = G_SUB [[UV1]], [[UV3]]106 ; SSE2-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<16 x s16>) = G_CONCAT_VECTORS [[SUB]](<8 x s16>), [[SUB1]](<8 x s16>)107 ; SSE2-NEXT: $ymm0 = COPY [[CONCAT_VECTORS]](<16 x s16>)108 ; SSE2-NEXT: RET 0109 ;110 ; AVX1-LABEL: name: test_sub_v16i16111 ; AVX1: liveins: $ymm0, $ymm1112 ; AVX1-NEXT: {{ $}}113 ; AVX1-NEXT: [[DEF:%[0-9]+]]:_(<16 x s16>) = IMPLICIT_DEF114 ; AVX1-NEXT: [[DEF1:%[0-9]+]]:_(<16 x s16>) = IMPLICIT_DEF115 ; AVX1-NEXT: [[UV:%[0-9]+]]:_(<8 x s16>), [[UV1:%[0-9]+]]:_(<8 x s16>) = G_UNMERGE_VALUES [[DEF]](<16 x s16>)116 ; AVX1-NEXT: [[UV2:%[0-9]+]]:_(<8 x s16>), [[UV3:%[0-9]+]]:_(<8 x s16>) = G_UNMERGE_VALUES [[DEF1]](<16 x s16>)117 ; AVX1-NEXT: [[SUB:%[0-9]+]]:_(<8 x s16>) = G_SUB [[UV]], [[UV2]]118 ; AVX1-NEXT: [[SUB1:%[0-9]+]]:_(<8 x s16>) = G_SUB [[UV1]], [[UV3]]119 ; AVX1-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<16 x s16>) = G_CONCAT_VECTORS [[SUB]](<8 x s16>), [[SUB1]](<8 x s16>)120 ; AVX1-NEXT: $ymm0 = COPY [[CONCAT_VECTORS]](<16 x s16>)121 ; AVX1-NEXT: RET 0122 ;123 ; AVX2-LABEL: name: test_sub_v16i16124 ; AVX2: liveins: $ymm0, $ymm1125 ; AVX2-NEXT: {{ $}}126 ; AVX2-NEXT: [[DEF:%[0-9]+]]:_(<16 x s16>) = IMPLICIT_DEF127 ; AVX2-NEXT: [[DEF1:%[0-9]+]]:_(<16 x s16>) = IMPLICIT_DEF128 ; AVX2-NEXT: [[SUB:%[0-9]+]]:_(<16 x s16>) = G_SUB [[DEF]], [[DEF1]]129 ; AVX2-NEXT: $ymm0 = COPY [[SUB]](<16 x s16>)130 ; AVX2-NEXT: RET 0131 %0(<16 x s16>) = IMPLICIT_DEF132 %1(<16 x s16>) = IMPLICIT_DEF133 %2(<16 x s16>) = G_SUB %0, %1134 $ymm0 = COPY %2135 RET 0136 137...138---139name: test_sub_v8i32140alignment: 16141legalized: false142regBankSelected: false143registers:144 - { id: 0, class: _ }145 - { id: 1, class: _ }146 - { id: 2, class: _ }147body: |148 bb.1 (%ir-block.0):149 liveins: $ymm0, $ymm1150 151 ; SSE2-LABEL: name: test_sub_v8i32152 ; SSE2: liveins: $ymm0, $ymm1153 ; SSE2-NEXT: {{ $}}154 ; SSE2-NEXT: [[DEF:%[0-9]+]]:_(<8 x s32>) = IMPLICIT_DEF155 ; SSE2-NEXT: [[DEF1:%[0-9]+]]:_(<8 x s32>) = IMPLICIT_DEF156 ; SSE2-NEXT: [[UV:%[0-9]+]]:_(<4 x s32>), [[UV1:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[DEF]](<8 x s32>)157 ; SSE2-NEXT: [[UV2:%[0-9]+]]:_(<4 x s32>), [[UV3:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[DEF1]](<8 x s32>)158 ; SSE2-NEXT: [[SUB:%[0-9]+]]:_(<4 x s32>) = G_SUB [[UV]], [[UV2]]159 ; SSE2-NEXT: [[SUB1:%[0-9]+]]:_(<4 x s32>) = G_SUB [[UV1]], [[UV3]]160 ; SSE2-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s32>) = G_CONCAT_VECTORS [[SUB]](<4 x s32>), [[SUB1]](<4 x s32>)161 ; SSE2-NEXT: $ymm0 = COPY [[CONCAT_VECTORS]](<8 x s32>)162 ; SSE2-NEXT: RET 0163 ;164 ; AVX1-LABEL: name: test_sub_v8i32165 ; AVX1: liveins: $ymm0, $ymm1166 ; AVX1-NEXT: {{ $}}167 ; AVX1-NEXT: [[DEF:%[0-9]+]]:_(<8 x s32>) = IMPLICIT_DEF168 ; AVX1-NEXT: [[DEF1:%[0-9]+]]:_(<8 x s32>) = IMPLICIT_DEF169 ; AVX1-NEXT: [[UV:%[0-9]+]]:_(<4 x s32>), [[UV1:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[DEF]](<8 x s32>)170 ; AVX1-NEXT: [[UV2:%[0-9]+]]:_(<4 x s32>), [[UV3:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[DEF1]](<8 x s32>)171 ; AVX1-NEXT: [[SUB:%[0-9]+]]:_(<4 x s32>) = G_SUB [[UV]], [[UV2]]172 ; AVX1-NEXT: [[SUB1:%[0-9]+]]:_(<4 x s32>) = G_SUB [[UV1]], [[UV3]]173 ; AVX1-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s32>) = G_CONCAT_VECTORS [[SUB]](<4 x s32>), [[SUB1]](<4 x s32>)174 ; AVX1-NEXT: $ymm0 = COPY [[CONCAT_VECTORS]](<8 x s32>)175 ; AVX1-NEXT: RET 0176 ;177 ; AVX2-LABEL: name: test_sub_v8i32178 ; AVX2: liveins: $ymm0, $ymm1179 ; AVX2-NEXT: {{ $}}180 ; AVX2-NEXT: [[DEF:%[0-9]+]]:_(<8 x s32>) = IMPLICIT_DEF181 ; AVX2-NEXT: [[DEF1:%[0-9]+]]:_(<8 x s32>) = IMPLICIT_DEF182 ; AVX2-NEXT: [[SUB:%[0-9]+]]:_(<8 x s32>) = G_SUB [[DEF]], [[DEF1]]183 ; AVX2-NEXT: $ymm0 = COPY [[SUB]](<8 x s32>)184 ; AVX2-NEXT: RET 0185 %0(<8 x s32>) = IMPLICIT_DEF186 %1(<8 x s32>) = IMPLICIT_DEF187 %2(<8 x s32>) = G_SUB %0, %1188 $ymm0 = COPY %2189 RET 0190 191...192---193name: test_sub_v4i64194alignment: 16195legalized: false196regBankSelected: false197registers:198 - { id: 0, class: _ }199 - { id: 1, class: _ }200 - { id: 2, class: _ }201body: |202 bb.1 (%ir-block.0):203 liveins: $ymm0, $ymm1204 205 ; SSE2-LABEL: name: test_sub_v4i64206 ; SSE2: liveins: $ymm0, $ymm1207 ; SSE2-NEXT: {{ $}}208 ; SSE2-NEXT: [[DEF:%[0-9]+]]:_(<4 x s64>) = IMPLICIT_DEF209 ; SSE2-NEXT: [[DEF1:%[0-9]+]]:_(<4 x s64>) = IMPLICIT_DEF210 ; SSE2-NEXT: [[UV:%[0-9]+]]:_(<2 x s64>), [[UV1:%[0-9]+]]:_(<2 x s64>) = G_UNMERGE_VALUES [[DEF]](<4 x s64>)211 ; SSE2-NEXT: [[UV2:%[0-9]+]]:_(<2 x s64>), [[UV3:%[0-9]+]]:_(<2 x s64>) = G_UNMERGE_VALUES [[DEF1]](<4 x s64>)212 ; SSE2-NEXT: [[SUB:%[0-9]+]]:_(<2 x s64>) = G_SUB [[UV]], [[UV2]]213 ; SSE2-NEXT: [[SUB1:%[0-9]+]]:_(<2 x s64>) = G_SUB [[UV1]], [[UV3]]214 ; SSE2-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s64>) = G_CONCAT_VECTORS [[SUB]](<2 x s64>), [[SUB1]](<2 x s64>)215 ; SSE2-NEXT: $ymm0 = COPY [[CONCAT_VECTORS]](<4 x s64>)216 ; SSE2-NEXT: RET 0217 ;218 ; AVX1-LABEL: name: test_sub_v4i64219 ; AVX1: liveins: $ymm0, $ymm1220 ; AVX1-NEXT: {{ $}}221 ; AVX1-NEXT: [[DEF:%[0-9]+]]:_(<4 x s64>) = IMPLICIT_DEF222 ; AVX1-NEXT: [[DEF1:%[0-9]+]]:_(<4 x s64>) = IMPLICIT_DEF223 ; AVX1-NEXT: [[UV:%[0-9]+]]:_(<2 x s64>), [[UV1:%[0-9]+]]:_(<2 x s64>) = G_UNMERGE_VALUES [[DEF]](<4 x s64>)224 ; AVX1-NEXT: [[UV2:%[0-9]+]]:_(<2 x s64>), [[UV3:%[0-9]+]]:_(<2 x s64>) = G_UNMERGE_VALUES [[DEF1]](<4 x s64>)225 ; AVX1-NEXT: [[SUB:%[0-9]+]]:_(<2 x s64>) = G_SUB [[UV]], [[UV2]]226 ; AVX1-NEXT: [[SUB1:%[0-9]+]]:_(<2 x s64>) = G_SUB [[UV1]], [[UV3]]227 ; AVX1-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s64>) = G_CONCAT_VECTORS [[SUB]](<2 x s64>), [[SUB1]](<2 x s64>)228 ; AVX1-NEXT: $ymm0 = COPY [[CONCAT_VECTORS]](<4 x s64>)229 ; AVX1-NEXT: RET 0230 ;231 ; AVX2-LABEL: name: test_sub_v4i64232 ; AVX2: liveins: $ymm0, $ymm1233 ; AVX2-NEXT: {{ $}}234 ; AVX2-NEXT: [[DEF:%[0-9]+]]:_(<4 x s64>) = IMPLICIT_DEF235 ; AVX2-NEXT: [[DEF1:%[0-9]+]]:_(<4 x s64>) = IMPLICIT_DEF236 ; AVX2-NEXT: [[SUB:%[0-9]+]]:_(<4 x s64>) = G_SUB [[DEF]], [[DEF1]]237 ; AVX2-NEXT: $ymm0 = COPY [[SUB]](<4 x s64>)238 ; AVX2-NEXT: RET 0239 %0(<4 x s64>) = IMPLICIT_DEF240 %1(<4 x s64>) = IMPLICIT_DEF241 %2(<4 x s64>) = G_SUB %0, %1242 $ymm0 = COPY %2243 RET 0244 245...246