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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=AVX13# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=AVX512F4# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f,+avx512bw -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=AVX512BW5 6# TODO: add tests for additional configuration after the legalization supported7 8--- |9 define void @test_sub_v64i8() {10 %ret = sub <64 x i8> undef, undef11 ret void12 }13 14 define void @test_sub_v32i16() {15 %ret = sub <32 x i16> undef, undef16 ret void17 }18 19 define void @test_sub_v16i32() {20 %ret = sub <16 x i32> undef, undef21 ret void22 }23 24 define void @test_sub_v8i64() {25 %ret = sub <8 x i64> undef, undef26 ret void27 }28 29...30---31name: test_sub_v64i832alignment: 1633legalized: false34regBankSelected: false35registers:36 - { id: 0, class: _ }37 - { id: 1, class: _ }38 - { id: 2, class: _ }39body: |40 bb.1 (%ir-block.0):41 liveins: $zmm0, $zmm142 43 ; AVX1-LABEL: name: test_sub_v64i844 ; AVX1: liveins: $zmm0, $zmm145 ; AVX1-NEXT: {{ $}}46 ; AVX1-NEXT: [[DEF:%[0-9]+]]:_(<64 x s8>) = IMPLICIT_DEF47 ; AVX1-NEXT: [[DEF1:%[0-9]+]]:_(<64 x s8>) = IMPLICIT_DEF48 ; AVX1-NEXT: [[UV:%[0-9]+]]:_(<16 x s8>), [[UV1:%[0-9]+]]:_(<16 x s8>), [[UV2:%[0-9]+]]:_(<16 x s8>), [[UV3:%[0-9]+]]:_(<16 x s8>) = G_UNMERGE_VALUES [[DEF]](<64 x s8>)49 ; AVX1-NEXT: [[UV4:%[0-9]+]]:_(<16 x s8>), [[UV5:%[0-9]+]]:_(<16 x s8>), [[UV6:%[0-9]+]]:_(<16 x s8>), [[UV7:%[0-9]+]]:_(<16 x s8>) = G_UNMERGE_VALUES [[DEF1]](<64 x s8>)50 ; AVX1-NEXT: [[SUB:%[0-9]+]]:_(<16 x s8>) = G_SUB [[UV]], [[UV4]]51 ; AVX1-NEXT: [[SUB1:%[0-9]+]]:_(<16 x s8>) = G_SUB [[UV1]], [[UV5]]52 ; AVX1-NEXT: [[SUB2:%[0-9]+]]:_(<16 x s8>) = G_SUB [[UV2]], [[UV6]]53 ; AVX1-NEXT: [[SUB3:%[0-9]+]]:_(<16 x s8>) = G_SUB [[UV3]], [[UV7]]54 ; AVX1-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<64 x s8>) = G_CONCAT_VECTORS [[SUB]](<16 x s8>), [[SUB1]](<16 x s8>), [[SUB2]](<16 x s8>), [[SUB3]](<16 x s8>)55 ; AVX1-NEXT: $zmm0 = COPY [[CONCAT_VECTORS]](<64 x s8>)56 ; AVX1-NEXT: RET 057 ;58 ; AVX512F-LABEL: name: test_sub_v64i859 ; AVX512F: liveins: $zmm0, $zmm160 ; AVX512F-NEXT: {{ $}}61 ; AVX512F-NEXT: [[DEF:%[0-9]+]]:_(<64 x s8>) = IMPLICIT_DEF62 ; AVX512F-NEXT: [[DEF1:%[0-9]+]]:_(<64 x s8>) = IMPLICIT_DEF63 ; AVX512F-NEXT: [[UV:%[0-9]+]]:_(<32 x s8>), [[UV1:%[0-9]+]]:_(<32 x s8>) = G_UNMERGE_VALUES [[DEF]](<64 x s8>)64 ; AVX512F-NEXT: [[UV2:%[0-9]+]]:_(<32 x s8>), [[UV3:%[0-9]+]]:_(<32 x s8>) = G_UNMERGE_VALUES [[DEF1]](<64 x s8>)65 ; AVX512F-NEXT: [[SUB:%[0-9]+]]:_(<32 x s8>) = G_SUB [[UV]], [[UV2]]66 ; AVX512F-NEXT: [[SUB1:%[0-9]+]]:_(<32 x s8>) = G_SUB [[UV1]], [[UV3]]67 ; AVX512F-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<64 x s8>) = G_CONCAT_VECTORS [[SUB]](<32 x s8>), [[SUB1]](<32 x s8>)68 ; AVX512F-NEXT: $zmm0 = COPY [[CONCAT_VECTORS]](<64 x s8>)69 ; AVX512F-NEXT: RET 070 ;71 ; AVX512BW-LABEL: name: test_sub_v64i872 ; AVX512BW: liveins: $zmm0, $zmm173 ; AVX512BW-NEXT: {{ $}}74 ; AVX512BW-NEXT: [[DEF:%[0-9]+]]:_(<64 x s8>) = IMPLICIT_DEF75 ; AVX512BW-NEXT: [[DEF1:%[0-9]+]]:_(<64 x s8>) = IMPLICIT_DEF76 ; AVX512BW-NEXT: [[SUB:%[0-9]+]]:_(<64 x s8>) = G_SUB [[DEF]], [[DEF1]]77 ; AVX512BW-NEXT: $zmm0 = COPY [[SUB]](<64 x s8>)78 ; AVX512BW-NEXT: RET 079 %0(<64 x s8>) = IMPLICIT_DEF80 %1(<64 x s8>) = IMPLICIT_DEF81 %2(<64 x s8>) = G_SUB %0, %182 $zmm0 = COPY %283 RET 084 85...86---87name: test_sub_v32i1688alignment: 1689legalized: false90regBankSelected: false91registers:92 - { id: 0, class: _ }93 - { id: 1, class: _ }94 - { id: 2, class: _ }95body: |96 bb.1 (%ir-block.0):97 liveins: $zmm0, $zmm198 99 ; AVX1-LABEL: name: test_sub_v32i16100 ; AVX1: liveins: $zmm0, $zmm1101 ; AVX1-NEXT: {{ $}}102 ; AVX1-NEXT: [[DEF:%[0-9]+]]:_(<32 x s16>) = IMPLICIT_DEF103 ; AVX1-NEXT: [[DEF1:%[0-9]+]]:_(<32 x s16>) = IMPLICIT_DEF104 ; AVX1-NEXT: [[UV:%[0-9]+]]:_(<8 x s16>), [[UV1:%[0-9]+]]:_(<8 x s16>), [[UV2:%[0-9]+]]:_(<8 x s16>), [[UV3:%[0-9]+]]:_(<8 x s16>) = G_UNMERGE_VALUES [[DEF]](<32 x s16>)105 ; AVX1-NEXT: [[UV4:%[0-9]+]]:_(<8 x s16>), [[UV5:%[0-9]+]]:_(<8 x s16>), [[UV6:%[0-9]+]]:_(<8 x s16>), [[UV7:%[0-9]+]]:_(<8 x s16>) = G_UNMERGE_VALUES [[DEF1]](<32 x s16>)106 ; AVX1-NEXT: [[SUB:%[0-9]+]]:_(<8 x s16>) = G_SUB [[UV]], [[UV4]]107 ; AVX1-NEXT: [[SUB1:%[0-9]+]]:_(<8 x s16>) = G_SUB [[UV1]], [[UV5]]108 ; AVX1-NEXT: [[SUB2:%[0-9]+]]:_(<8 x s16>) = G_SUB [[UV2]], [[UV6]]109 ; AVX1-NEXT: [[SUB3:%[0-9]+]]:_(<8 x s16>) = G_SUB [[UV3]], [[UV7]]110 ; AVX1-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<32 x s16>) = G_CONCAT_VECTORS [[SUB]](<8 x s16>), [[SUB1]](<8 x s16>), [[SUB2]](<8 x s16>), [[SUB3]](<8 x s16>)111 ; AVX1-NEXT: $zmm0 = COPY [[CONCAT_VECTORS]](<32 x s16>)112 ; AVX1-NEXT: RET 0113 ;114 ; AVX512F-LABEL: name: test_sub_v32i16115 ; AVX512F: liveins: $zmm0, $zmm1116 ; AVX512F-NEXT: {{ $}}117 ; AVX512F-NEXT: [[DEF:%[0-9]+]]:_(<32 x s16>) = IMPLICIT_DEF118 ; AVX512F-NEXT: [[DEF1:%[0-9]+]]:_(<32 x s16>) = IMPLICIT_DEF119 ; AVX512F-NEXT: [[UV:%[0-9]+]]:_(<16 x s16>), [[UV1:%[0-9]+]]:_(<16 x s16>) = G_UNMERGE_VALUES [[DEF]](<32 x s16>)120 ; AVX512F-NEXT: [[UV2:%[0-9]+]]:_(<16 x s16>), [[UV3:%[0-9]+]]:_(<16 x s16>) = G_UNMERGE_VALUES [[DEF1]](<32 x s16>)121 ; AVX512F-NEXT: [[SUB:%[0-9]+]]:_(<16 x s16>) = G_SUB [[UV]], [[UV2]]122 ; AVX512F-NEXT: [[SUB1:%[0-9]+]]:_(<16 x s16>) = G_SUB [[UV1]], [[UV3]]123 ; AVX512F-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<32 x s16>) = G_CONCAT_VECTORS [[SUB]](<16 x s16>), [[SUB1]](<16 x s16>)124 ; AVX512F-NEXT: $zmm0 = COPY [[CONCAT_VECTORS]](<32 x s16>)125 ; AVX512F-NEXT: RET 0126 ;127 ; AVX512BW-LABEL: name: test_sub_v32i16128 ; AVX512BW: liveins: $zmm0, $zmm1129 ; AVX512BW-NEXT: {{ $}}130 ; AVX512BW-NEXT: [[DEF:%[0-9]+]]:_(<32 x s16>) = IMPLICIT_DEF131 ; AVX512BW-NEXT: [[DEF1:%[0-9]+]]:_(<32 x s16>) = IMPLICIT_DEF132 ; AVX512BW-NEXT: [[SUB:%[0-9]+]]:_(<32 x s16>) = G_SUB [[DEF]], [[DEF1]]133 ; AVX512BW-NEXT: $zmm0 = COPY [[SUB]](<32 x s16>)134 ; AVX512BW-NEXT: RET 0135 %0(<32 x s16>) = IMPLICIT_DEF136 %1(<32 x s16>) = IMPLICIT_DEF137 %2(<32 x s16>) = G_SUB %0, %1138 $zmm0 = COPY %2139 RET 0140 141...142---143name: test_sub_v16i32144alignment: 16145legalized: false146regBankSelected: false147registers:148 - { id: 0, class: _ }149 - { id: 1, class: _ }150 - { id: 2, class: _ }151body: |152 bb.1 (%ir-block.0):153 liveins: $zmm0, $zmm1154 155 ; AVX1-LABEL: name: test_sub_v16i32156 ; AVX1: liveins: $zmm0, $zmm1157 ; AVX1-NEXT: {{ $}}158 ; AVX1-NEXT: [[DEF:%[0-9]+]]:_(<16 x s32>) = IMPLICIT_DEF159 ; AVX1-NEXT: [[DEF1:%[0-9]+]]:_(<16 x s32>) = IMPLICIT_DEF160 ; AVX1-NEXT: [[UV:%[0-9]+]]:_(<4 x s32>), [[UV1:%[0-9]+]]:_(<4 x s32>), [[UV2:%[0-9]+]]:_(<4 x s32>), [[UV3:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[DEF]](<16 x s32>)161 ; AVX1-NEXT: [[UV4:%[0-9]+]]:_(<4 x s32>), [[UV5:%[0-9]+]]:_(<4 x s32>), [[UV6:%[0-9]+]]:_(<4 x s32>), [[UV7:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[DEF1]](<16 x s32>)162 ; AVX1-NEXT: [[SUB:%[0-9]+]]:_(<4 x s32>) = G_SUB [[UV]], [[UV4]]163 ; AVX1-NEXT: [[SUB1:%[0-9]+]]:_(<4 x s32>) = G_SUB [[UV1]], [[UV5]]164 ; AVX1-NEXT: [[SUB2:%[0-9]+]]:_(<4 x s32>) = G_SUB [[UV2]], [[UV6]]165 ; AVX1-NEXT: [[SUB3:%[0-9]+]]:_(<4 x s32>) = G_SUB [[UV3]], [[UV7]]166 ; AVX1-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<16 x s32>) = G_CONCAT_VECTORS [[SUB]](<4 x s32>), [[SUB1]](<4 x s32>), [[SUB2]](<4 x s32>), [[SUB3]](<4 x s32>)167 ; AVX1-NEXT: $zmm0 = COPY [[CONCAT_VECTORS]](<16 x s32>)168 ; AVX1-NEXT: RET 0169 ;170 ; AVX512F-LABEL: name: test_sub_v16i32171 ; AVX512F: liveins: $zmm0, $zmm1172 ; AVX512F-NEXT: {{ $}}173 ; AVX512F-NEXT: [[DEF:%[0-9]+]]:_(<16 x s32>) = IMPLICIT_DEF174 ; AVX512F-NEXT: [[DEF1:%[0-9]+]]:_(<16 x s32>) = IMPLICIT_DEF175 ; AVX512F-NEXT: [[SUB:%[0-9]+]]:_(<16 x s32>) = G_SUB [[DEF]], [[DEF1]]176 ; AVX512F-NEXT: $zmm0 = COPY [[SUB]](<16 x s32>)177 ; AVX512F-NEXT: RET 0178 ;179 ; AVX512BW-LABEL: name: test_sub_v16i32180 ; AVX512BW: liveins: $zmm0, $zmm1181 ; AVX512BW-NEXT: {{ $}}182 ; AVX512BW-NEXT: [[DEF:%[0-9]+]]:_(<16 x s32>) = IMPLICIT_DEF183 ; AVX512BW-NEXT: [[DEF1:%[0-9]+]]:_(<16 x s32>) = IMPLICIT_DEF184 ; AVX512BW-NEXT: [[SUB:%[0-9]+]]:_(<16 x s32>) = G_SUB [[DEF]], [[DEF1]]185 ; AVX512BW-NEXT: $zmm0 = COPY [[SUB]](<16 x s32>)186 ; AVX512BW-NEXT: RET 0187 %0(<16 x s32>) = IMPLICIT_DEF188 %1(<16 x s32>) = IMPLICIT_DEF189 %2(<16 x s32>) = G_SUB %0, %1190 $zmm0 = COPY %2191 RET 0192 193...194---195name: test_sub_v8i64196alignment: 16197legalized: false198regBankSelected: false199registers:200 - { id: 0, class: _ }201 - { id: 1, class: _ }202 - { id: 2, class: _ }203body: |204 bb.1 (%ir-block.0):205 liveins: $zmm0, $zmm1206 207 ; AVX1-LABEL: name: test_sub_v8i64208 ; AVX1: liveins: $zmm0, $zmm1209 ; AVX1-NEXT: {{ $}}210 ; AVX1-NEXT: [[DEF:%[0-9]+]]:_(<8 x s64>) = IMPLICIT_DEF211 ; AVX1-NEXT: [[DEF1:%[0-9]+]]:_(<8 x s64>) = IMPLICIT_DEF212 ; AVX1-NEXT: [[UV:%[0-9]+]]:_(<2 x s64>), [[UV1:%[0-9]+]]:_(<2 x s64>), [[UV2:%[0-9]+]]:_(<2 x s64>), [[UV3:%[0-9]+]]:_(<2 x s64>) = G_UNMERGE_VALUES [[DEF]](<8 x s64>)213 ; AVX1-NEXT: [[UV4:%[0-9]+]]:_(<2 x s64>), [[UV5:%[0-9]+]]:_(<2 x s64>), [[UV6:%[0-9]+]]:_(<2 x s64>), [[UV7:%[0-9]+]]:_(<2 x s64>) = G_UNMERGE_VALUES [[DEF1]](<8 x s64>)214 ; AVX1-NEXT: [[SUB:%[0-9]+]]:_(<2 x s64>) = G_SUB [[UV]], [[UV4]]215 ; AVX1-NEXT: [[SUB1:%[0-9]+]]:_(<2 x s64>) = G_SUB [[UV1]], [[UV5]]216 ; AVX1-NEXT: [[SUB2:%[0-9]+]]:_(<2 x s64>) = G_SUB [[UV2]], [[UV6]]217 ; AVX1-NEXT: [[SUB3:%[0-9]+]]:_(<2 x s64>) = G_SUB [[UV3]], [[UV7]]218 ; AVX1-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s64>) = G_CONCAT_VECTORS [[SUB]](<2 x s64>), [[SUB1]](<2 x s64>), [[SUB2]](<2 x s64>), [[SUB3]](<2 x s64>)219 ; AVX1-NEXT: $zmm0 = COPY [[CONCAT_VECTORS]](<8 x s64>)220 ; AVX1-NEXT: RET 0221 ;222 ; AVX512F-LABEL: name: test_sub_v8i64223 ; AVX512F: liveins: $zmm0, $zmm1224 ; AVX512F-NEXT: {{ $}}225 ; AVX512F-NEXT: [[DEF:%[0-9]+]]:_(<8 x s64>) = IMPLICIT_DEF226 ; AVX512F-NEXT: [[DEF1:%[0-9]+]]:_(<8 x s64>) = IMPLICIT_DEF227 ; AVX512F-NEXT: [[SUB:%[0-9]+]]:_(<8 x s64>) = G_SUB [[DEF]], [[DEF1]]228 ; AVX512F-NEXT: $zmm0 = COPY [[SUB]](<8 x s64>)229 ; AVX512F-NEXT: RET 0230 ;231 ; AVX512BW-LABEL: name: test_sub_v8i64232 ; AVX512BW: liveins: $zmm0, $zmm1233 ; AVX512BW-NEXT: {{ $}}234 ; AVX512BW-NEXT: [[DEF:%[0-9]+]]:_(<8 x s64>) = IMPLICIT_DEF235 ; AVX512BW-NEXT: [[DEF1:%[0-9]+]]:_(<8 x s64>) = IMPLICIT_DEF236 ; AVX512BW-NEXT: [[SUB:%[0-9]+]]:_(<8 x s64>) = G_SUB [[DEF]], [[DEF1]]237 ; AVX512BW-NEXT: $zmm0 = COPY [[SUB]](<8 x s64>)238 ; AVX512BW-NEXT: RET 0239 %0(<8 x s64>) = IMPLICIT_DEF240 %1(<8 x s64>) = IMPLICIT_DEF241 %2(<8 x s64>) = G_SUB %0, %1242 $zmm0 = COPY %2243 RET 0244 245...246