250 lines · plain
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -O0 -mtriple=x86_64-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=CHECK,X643# RUN: llc -O0 -mtriple=i386-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=CHECK,X864 5--- |6 7 define void @test_sub_i1() { ret void}8 define void @test_sub_i8() { ret void }9 define void @test_sub_i16() { ret void }10 define void @test_sub_i27() { ret void }11 define void @test_sub_i32() { ret void }12 define void @test_sub_i42() { ret void }13 define void @test_sub_i64() { ret void }14 define void @test_sub_i128() { ret void }15 16...17---18name: test_sub_i119alignment: 1620legalized: false21regBankSelected: false22registers:23 - { id: 0, class: _, preferred-register: '' }24 - { id: 1, class: _, preferred-register: '' }25 - { id: 2, class: _, preferred-register: '' }26body: |27 bb.1 (%ir-block.0):28 ; CHECK-LABEL: name: test_sub_i129 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edx30 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)31 ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)32 ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s8) = G_SUB [[TRUNC]], [[TRUNC1]]33 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SUB]](s8)34 ; CHECK-NEXT: $eax = COPY [[ANYEXT]](s32)35 ; CHECK-NEXT: RET 036 %0(s32) = COPY $edx37 %1(s1) = G_TRUNC %0(s32)38 %2(s1) = G_SUB %1, %139 %3:_(s32) = G_ANYEXT %240 $eax = COPY %341 RET 042...43---44name: test_sub_i845alignment: 1646legalized: false47regBankSelected: false48registers:49 - { id: 0, class: _, preferred-register: '' }50 - { id: 1, class: _, preferred-register: '' }51 - { id: 2, class: _, preferred-register: '' }52body: |53 bb.1 (%ir-block.0):54 ; CHECK-LABEL: name: test_sub_i855 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edx56 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)57 ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s8) = G_SUB [[TRUNC]], [[TRUNC]]58 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SUB]](s8)59 ; CHECK-NEXT: $eax = COPY [[ANYEXT]](s32)60 ; CHECK-NEXT: RET 061 %0(s32) = COPY $edx62 %1(s8) = G_TRUNC %0(s32)63 %2(s8) = G_SUB %1, %164 %3:_(s32) = G_ANYEXT %265 $eax = COPY %366 RET 067...68---69name: test_sub_i1670alignment: 1671legalized: false72regBankSelected: false73registers:74 - { id: 0, class: _ }75 - { id: 1, class: _ }76 - { id: 2, class: _ }77body: |78 bb.1 (%ir-block.0):79 ; CHECK-LABEL: name: test_sub_i1680 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edx81 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)82 ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s16) = G_SUB [[TRUNC]], [[TRUNC]]83 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SUB]](s16)84 ; CHECK-NEXT: $eax = COPY [[ANYEXT]](s32)85 ; CHECK-NEXT: RET 086 %0(s32) = COPY $edx87 %1(s16) = G_TRUNC %0(s32)88 %2(s16) = G_SUB %1, %189 %3:_(s32) = G_ANYEXT %290 $eax = COPY %391 RET 092...93---94name: test_sub_i2795alignment: 1696legalized: false97regBankSelected: false98registers:99 - { id: 0, class: _ }100 - { id: 1, class: _ }101 - { id: 2, class: _ }102body: |103 bb.1 (%ir-block.0):104 ; CHECK-LABEL: name: test_sub_i27105 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edx106 ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[COPY]]107 ; CHECK-NEXT: $eax = COPY [[SUB]](s32)108 ; CHECK-NEXT: RET 0109 %0(s32) = COPY $edx110 %1(s27) = G_TRUNC %0(s32)111 %2(s27) = G_SUB %1, %1112 %3:_(s32) = G_ANYEXT %2113 $eax = COPY %3114 RET 0115...116---117name: test_sub_i32118alignment: 16119legalized: false120regBankSelected: false121registers:122 - { id: 0, class: _ }123 - { id: 1, class: _ }124 - { id: 2, class: _ }125body: |126 bb.1 (%ir-block.0):127 ; CHECK-LABEL: name: test_sub_i32128 ; CHECK: [[DEF:%[0-9]+]]:_(s32) = IMPLICIT_DEF129 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s32) = IMPLICIT_DEF130 ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[DEF]], [[DEF1]]131 ; CHECK-NEXT: $eax = COPY [[SUB]](s32)132 ; CHECK-NEXT: RET 0133 %0(s32) = IMPLICIT_DEF134 %1(s32) = IMPLICIT_DEF135 %2(s32) = G_SUB %0, %1136 $eax = COPY %2137 RET 0138...139---140name: test_sub_i42141alignment: 16142legalized: false143regBankSelected: false144registers:145 - { id: 0, class: _ }146 - { id: 1, class: _ }147 - { id: 2, class: _ }148body: |149 bb.1 (%ir-block.0):150 ; X64-LABEL: name: test_sub_i42151 ; X64: [[COPY:%[0-9]+]]:_(s64) = COPY $rdx152 ; X64-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[COPY]], [[COPY]]153 ; X64-NEXT: $rax = COPY [[SUB]](s64)154 ; X64-NEXT: RET 0155 ;156 ; X86-LABEL: name: test_sub_i42157 ; X86: [[COPY:%[0-9]+]]:_(s64) = COPY $rdx158 ; X86-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)159 ; X86-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)160 ; X86-NEXT: [[USUBO:%[0-9]+]]:_(s32), [[USUBO1:%[0-9]+]]:_(s8) = G_USUBO [[UV]], [[UV2]]161 ; X86-NEXT: [[USUBE:%[0-9]+]]:_(s32), [[USUBE1:%[0-9]+]]:_(s8) = G_USUBE [[UV1]], [[UV3]], [[USUBO1]]162 ; X86-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO]](s32), [[USUBE]](s32)163 ; X86-NEXT: $rax = COPY [[MV]](s64)164 ; X86-NEXT: RET 0165 %0(s64) = COPY $rdx166 %1(s42) = G_TRUNC %0(s64)167 %2(s42) = G_SUB %1, %1168 %3:_(s64) = G_ANYEXT %2169 $rax = COPY %3170 RET 0171...172---173name: test_sub_i64174alignment: 16175legalized: false176regBankSelected: false177registers:178 - { id: 0, class: _ }179 - { id: 1, class: _ }180 - { id: 2, class: _ }181body: |182 bb.1 (%ir-block.0):183 ; X64-LABEL: name: test_sub_i64184 ; X64: [[DEF:%[0-9]+]]:_(s64) = IMPLICIT_DEF185 ; X64-NEXT: [[DEF1:%[0-9]+]]:_(s64) = IMPLICIT_DEF186 ; X64-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[DEF]], [[DEF1]]187 ; X64-NEXT: $rax = COPY [[SUB]](s64)188 ; X64-NEXT: RET 0189 ;190 ; X86-LABEL: name: test_sub_i64191 ; X86: [[DEF:%[0-9]+]]:_(s64) = IMPLICIT_DEF192 ; X86-NEXT: [[DEF1:%[0-9]+]]:_(s64) = IMPLICIT_DEF193 ; X86-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](s64)194 ; X86-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF1]](s64)195 ; X86-NEXT: [[USUBO:%[0-9]+]]:_(s32), [[USUBO1:%[0-9]+]]:_(s8) = G_USUBO [[UV]], [[UV2]]196 ; X86-NEXT: [[USUBE:%[0-9]+]]:_(s32), [[USUBE1:%[0-9]+]]:_(s8) = G_USUBE [[UV1]], [[UV3]], [[USUBO1]]197 ; X86-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO]](s32), [[USUBE]](s32)198 ; X86-NEXT: $rax = COPY [[MV]](s64)199 ; X86-NEXT: RET 0200 %0(s64) = IMPLICIT_DEF201 %1(s64) = IMPLICIT_DEF202 %2(s64) = G_SUB %0, %1203 $rax = COPY %2204 RET 0205...206---207name: test_sub_i128208alignment: 16209legalized: false210regBankSelected: false211registers:212 - { id: 0, class: _ }213 - { id: 1, class: _ }214 - { id: 2, class: _ }215body: |216 bb.1 (%ir-block.0):217 ; X64-LABEL: name: test_sub_i128218 ; X64: [[DEF:%[0-9]+]]:_(s128) = IMPLICIT_DEF219 ; X64-NEXT: [[DEF1:%[0-9]+]]:_(s128) = IMPLICIT_DEF220 ; X64-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[DEF]](s128)221 ; X64-NEXT: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[DEF1]](s128)222 ; X64-NEXT: [[USUBO:%[0-9]+]]:_(s64), [[USUBO1:%[0-9]+]]:_(s8) = G_USUBO [[UV]], [[UV2]]223 ; X64-NEXT: [[USUBE:%[0-9]+]]:_(s64), [[USUBE1:%[0-9]+]]:_(s8) = G_USUBE [[UV1]], [[UV3]], [[USUBO1]]224 ; X64-NEXT: $rax = COPY [[USUBO]](s64)225 ; X64-NEXT: $rdx = COPY [[USUBE]](s64)226 ; X64-NEXT: RET 0227 ;228 ; X86-LABEL: name: test_sub_i128229 ; X86: [[DEF:%[0-9]+]]:_(s128) = IMPLICIT_DEF230 ; X86-NEXT: [[DEF1:%[0-9]+]]:_(s128) = IMPLICIT_DEF231 ; X86-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](s128)232 ; X86-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF1]](s128)233 ; X86-NEXT: [[USUBO:%[0-9]+]]:_(s32), [[USUBO1:%[0-9]+]]:_(s8) = G_USUBO [[UV]], [[UV4]]234 ; X86-NEXT: [[USUBE:%[0-9]+]]:_(s32), [[USUBE1:%[0-9]+]]:_(s8) = G_USUBE [[UV1]], [[UV5]], [[USUBO1]]235 ; X86-NEXT: [[USUBE2:%[0-9]+]]:_(s32), [[USUBE3:%[0-9]+]]:_(s8) = G_USUBE [[UV2]], [[UV6]], [[USUBE1]]236 ; X86-NEXT: [[USUBE4:%[0-9]+]]:_(s32), [[USUBE5:%[0-9]+]]:_(s8) = G_USUBE [[UV3]], [[UV7]], [[USUBE3]]237 ; X86-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO]](s32), [[USUBE]](s32)238 ; X86-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBE2]](s32), [[USUBE4]](s32)239 ; X86-NEXT: $rax = COPY [[MV]](s64)240 ; X86-NEXT: $rdx = COPY [[MV1]](s64)241 ; X86-NEXT: RET 0242 %0(s128) = IMPLICIT_DEF243 %1(s128) = IMPLICIT_DEF244 %2(s128) = G_SUB %0, %1245 %3:_(s64), %4:_(s64) = G_UNMERGE_VALUES %2(s128)246 $rax = COPY %3247 $rdx = COPY %4248 RET 0249...250