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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+sse2 -run-pass=legalizer %s -o - | FileCheck %s3# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -run-pass=legalizer %s -o - | FileCheck %s4# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx2 -run-pass=legalizer %s -o - | FileCheck %s5 6--- |7 define void @test_xor_v16i8() {8 %ret = xor <16 x i8> undef, undef9 ret void10 }11 12 define void @test_xor_v8i16() {13 %ret = xor <8 x i16> undef, undef14 ret void15 }16 17 define void @test_xor_v4i32() {18 %ret = xor <4 x i32> undef, undef19 ret void20 }21 22 define void @test_xor_v2i64() {23 %ret = xor <2 x i64> undef, undef24 ret void25 }26...27---28name: test_xor_v16i829alignment: 1630legalized: false31regBankSelected: false32registers:33 - { id: 0, class: _ }34 - { id: 1, class: _ }35 - { id: 2, class: _ }36body: |37 bb.1 (%ir-block.0):38 liveins: $xmm0, $xmm139 40 ; CHECK-LABEL: name: test_xor_v16i841 ; CHECK: liveins: $xmm0, $xmm142 ; CHECK-NEXT: {{ $}}43 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF44 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF45 ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<16 x s8>) = G_XOR [[DEF]], [[DEF1]]46 ; CHECK-NEXT: $xmm0 = COPY [[XOR]](<16 x s8>)47 ; CHECK-NEXT: RET 048 %0(<16 x s8>) = IMPLICIT_DEF49 %1(<16 x s8>) = IMPLICIT_DEF50 %2(<16 x s8>) = G_XOR %0, %151 $xmm0 = COPY %252 RET 053...54---55name: test_xor_v8i1656alignment: 1657legalized: false58regBankSelected: false59registers:60 - { id: 0, class: _ }61 - { id: 1, class: _ }62 - { id: 2, class: _ }63body: |64 bb.1 (%ir-block.0):65 liveins: $xmm0, $xmm166 67 ; CHECK-LABEL: name: test_xor_v8i1668 ; CHECK: liveins: $xmm0, $xmm169 ; CHECK-NEXT: {{ $}}70 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF71 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF72 ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<8 x s16>) = G_XOR [[DEF]], [[DEF1]]73 ; CHECK-NEXT: $xmm0 = COPY [[XOR]](<8 x s16>)74 ; CHECK-NEXT: RET 075 %0(<8 x s16>) = IMPLICIT_DEF76 %1(<8 x s16>) = IMPLICIT_DEF77 %2(<8 x s16>) = G_XOR %0, %178 $xmm0 = COPY %279 RET 080...81---82name: test_xor_v4i3283alignment: 1684legalized: false85regBankSelected: false86registers:87 - { id: 0, class: _ }88 - { id: 1, class: _ }89 - { id: 2, class: _ }90body: |91 bb.1 (%ir-block.0):92 liveins: $xmm0, $xmm193 94 ; CHECK-LABEL: name: test_xor_v4i3295 ; CHECK: liveins: $xmm0, $xmm196 ; CHECK-NEXT: {{ $}}97 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF98 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF99 ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<4 x s32>) = G_XOR [[DEF]], [[DEF1]]100 ; CHECK-NEXT: $xmm0 = COPY [[XOR]](<4 x s32>)101 ; CHECK-NEXT: RET 0102 %0(<4 x s32>) = IMPLICIT_DEF103 %1(<4 x s32>) = IMPLICIT_DEF104 %2(<4 x s32>) = G_XOR %0, %1105 $xmm0 = COPY %2106 RET 0107...108---109name: test_xor_v2i64110alignment: 16111legalized: false112regBankSelected: false113registers:114 - { id: 0, class: _ }115 - { id: 1, class: _ }116 - { id: 2, class: _ }117body: |118 bb.1 (%ir-block.0):119 liveins: $xmm0, $xmm1120 121 ; CHECK-LABEL: name: test_xor_v2i64122 ; CHECK: liveins: $xmm0, $xmm1123 ; CHECK-NEXT: {{ $}}124 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF125 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF126 ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[DEF]], [[DEF1]]127 ; CHECK-NEXT: $xmm0 = COPY [[XOR]](<2 x s64>)128 ; CHECK-NEXT: RET 0129 %0(<2 x s64>) = IMPLICIT_DEF130 %1(<2 x s64>) = IMPLICIT_DEF131 %2(<2 x s64>) = G_XOR %0, %1132 $xmm0 = COPY %2133 RET 0134...135