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1# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx2 --global-isel -run-pass=regbankselect %s -o - | FileCheck %s2# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx2 --global-isel -regbankselect-greedy -run-pass=regbankselect %s -o - | FileCheck %s3 4--- |5 define void @test_mul_vec256() {6 ret void7 }8 9 define void @test_add_vec256() {10 ret void11 }12 13 define void @test_sub_vec256() {14 ret void15 }16 17 define <8 x i32> @test_load_v8i32_noalign(ptr %p1) {18 %r = load <8 x i32>, ptr %p1, align 119 ret <8 x i32> %r20 }21 22 define void @test_store_v8i32_noalign(<8 x i32> %val, ptr %p1) {23 store <8 x i32> %val, ptr %p1, align 124 ret void25 }26 27---28name: test_mul_vec25629alignment: 1630legalized: true31regBankSelected: false32selected: false33tracksRegLiveness: true34# CHECK-LABEL: name: test_mul_vec25635# CHECK: registers:36# CHECK: - { id: 0, class: vecr, preferred-register: '', flags: [ ] }37# CHECK: - { id: 1, class: vecr, preferred-register: '', flags: [ ] }38registers:39 - { id: 0, class: _ }40 - { id: 1, class: _ }41 - { id: 2, class: _ }42body: |43 bb.1 (%ir-block.0):44 45 %0(<8 x s32>) = IMPLICIT_DEF46 %1(<8 x s32>) = G_MUL %0, %047 RET 048 49...50---51name: test_add_vec25652alignment: 1653legalized: true54regBankSelected: false55selected: false56tracksRegLiveness: true57# CHECK-LABEL: name: test_add_vec25658# CHECK: registers:59# CHECK: - { id: 0, class: vecr, preferred-register: '', flags: [ ] }60# CHECK: - { id: 1, class: vecr, preferred-register: '', flags: [ ] }61registers:62 - { id: 0, class: _ }63 - { id: 1, class: _ }64 - { id: 2, class: _ }65body: |66 bb.1 (%ir-block.0):67 68 %0(<8 x s32>) = IMPLICIT_DEF69 %1(<8 x s32>) = G_ADD %0, %070 RET 071 72...73---74name: test_sub_vec25675alignment: 1676legalized: true77regBankSelected: false78selected: false79tracksRegLiveness: true80# CHECK-LABEL: name: test_sub_vec25681# CHECK: registers:82# CHECK: - { id: 0, class: vecr, preferred-register: '', flags: [ ] }83# CHECK: - { id: 1, class: vecr, preferred-register: '', flags: [ ] }84registers:85 - { id: 0, class: _ }86 - { id: 1, class: _ }87 - { id: 2, class: _ }88body: |89 bb.1 (%ir-block.0):90 91 %0(<8 x s32>) = IMPLICIT_DEF92 %1(<8 x s32>) = G_SUB %0, %093 RET 094 95...96---97name: test_load_v8i32_noalign98# CHECK-LABEL: name: test_load_v8i32_noalign99alignment: 16100legalized: true101regBankSelected: false102# CHECK: registers:103# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '', flags: [ ] }104# CHECK-NEXT: - { id: 1, class: vecr, preferred-register: '', flags: [ ] }105registers:106 - { id: 0, class: _ }107 - { id: 1, class: _ }108body: |109 bb.1 (%ir-block.0):110 liveins: $rdi111 112 %0(p0) = COPY $rdi113 %1(<8 x s32>) = G_LOAD %0(p0) :: (load (<8 x s32>) from %ir.p1, align 1)114 $ymm0 = COPY %1(<8 x s32>)115 RET 0, implicit $ymm0116 117...118---119name: test_store_v8i32_noalign120# CHECK-LABEL: name: test_store_v8i32_noalign121alignment: 16122legalized: true123regBankSelected: false124# CHECK: registers:125# CHECK-NEXT: - { id: 0, class: vecr, preferred-register: '', flags: [ ] }126# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '', flags: [ ] }127registers:128 - { id: 0, class: _ }129 - { id: 1, class: _ }130body: |131 bb.1 (%ir-block.0):132 liveins: $rdi, $ymm0133 134 %0(<8 x s32>) = COPY $ymm0135 %1(p0) = COPY $rdi136 G_STORE %0(<8 x s32>), %1(p0) :: (store (<8 x s32>) into %ir.p1, align 1)137 RET 0138 139...140