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1# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -run-pass=regbankselect %s -o - | FileCheck %s2# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -regbankselect-greedy -run-pass=regbankselect %s -o - | FileCheck %s3 4--- |5 6 define void @test_mul_vec512() {7 ret void8 }9 10 define void @test_add_vec512() {11 ret void12 }13 14 define void @test_sub_vec512() {15 ret void16 }17 18 define <16 x i32> @test_load_v16i32_noalign(ptr %p1) {19 %r = load <16 x i32>, ptr %p1, align 120 ret <16 x i32> %r21 }22 23 define void @test_store_v16i32_noalign(<16 x i32> %val, ptr %p1) {24 store <16 x i32> %val, ptr %p1, align 125 ret void26 }27 28...29---30name: test_mul_vec51231# CHECK-LABEL: name: test_mul_vec51232alignment: 1633legalized: true34regBankSelected: false35# CHECK: registers:36# CHECK-NEXT: - { id: 0, class: vecr, preferred-register: '', flags: [ ] }37# CHECK-NEXT: - { id: 1, class: vecr, preferred-register: '', flags: [ ] }38registers:39 - { id: 0, class: _ }40 - { id: 1, class: _ }41body: |42 bb.1 (%ir-block.0):43 44 %0(<16 x s32>) = IMPLICIT_DEF45 %1(<16 x s32>) = G_MUL %0, %046 RET 047 48...49---50name: test_add_vec51251# CHECK-LABEL: name: test_add_vec51252alignment: 1653legalized: true54regBankSelected: false55# CHECK: registers:56# CHECK-NEXT: - { id: 0, class: vecr, preferred-register: '', flags: [ ] }57# CHECK-NEXT: - { id: 1, class: vecr, preferred-register: '', flags: [ ] }58registers:59 - { id: 0, class: _ }60 - { id: 1, class: _ }61body: |62 bb.1 (%ir-block.0):63 64 %0(<16 x s32>) = IMPLICIT_DEF65 %1(<16 x s32>) = G_ADD %0, %066 RET 067 68...69---70name: test_sub_vec51271# CHECK-LABEL: name: test_sub_vec51272alignment: 1673legalized: true74regBankSelected: false75# CHECK: registers:76# CHECK-NEXT: - { id: 0, class: vecr, preferred-register: '', flags: [ ] }77# CHECK-NEXT: - { id: 1, class: vecr, preferred-register: '', flags: [ ] }78registers:79 - { id: 0, class: _ }80 - { id: 1, class: _ }81body: |82 bb.1 (%ir-block.0):83 84 %0(<16 x s32>) = IMPLICIT_DEF85 %1(<16 x s32>) = G_SUB %0, %086 RET 087...88---89 90name: test_load_v16i32_noalign91# CHECK-LABEL: name: test_load_v16i32_noalign92alignment: 1693legalized: true94regBankSelected: false95# CHECK: registers:96# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '', flags: [ ] }97# CHECK-NEXT: - { id: 1, class: vecr, preferred-register: '', flags: [ ] }98registers:99 - { id: 0, class: _ }100 - { id: 1, class: _ }101body: |102 bb.1 (%ir-block.0):103 liveins: $rdi104 105 %0(p0) = COPY $rdi106 %1(<16 x s32>) = G_LOAD %0(p0) :: (load (<16 x s32>) from %ir.p1, align 1)107 $zmm0 = COPY %1(<16 x s32>)108 RET 0, implicit $zmm0109 110...111---112name: test_store_v16i32_noalign113# CHECK-LABEL: name: test_store_v16i32_noalign114alignment: 16115legalized: true116regBankSelected: false117# CHECK: registers:118# CHECK-NEXT: - { id: 0, class: vecr, preferred-register: '', flags: [ ] }119# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '', flags: [ ] }120registers:121 - { id: 0, class: _ }122 - { id: 1, class: _ }123body: |124 bb.1 (%ir-block.0):125 liveins: $rdi, $zmm0126 127 %0(<16 x s32>) = COPY $zmm0128 %1(p0) = COPY $rdi129 G_STORE %0(<16 x s32>), %1(p0) :: (store (<16 x s32>) into %ir.p1, align 1)130 RET 0131 132...133