196 lines · plain
1# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+sse2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NOVL --check-prefix=SSE22# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NOVL --check-prefix=AVX13# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f,+avx512vl -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=AVX512VL4# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f,+avx512vl,+avx512bw -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=AVX512BWVL5 6--- |7 define <16 x i8> @test_add_v16i8(<16 x i8> %arg1, <16 x i8> %arg2) {8 %ret = add <16 x i8> %arg1, %arg29 ret <16 x i8> %ret10 }11 12 define <8 x i16> @test_add_v8i16(<8 x i16> %arg1, <8 x i16> %arg2) {13 %ret = add <8 x i16> %arg1, %arg214 ret <8 x i16> %ret15 }16 17 define <4 x i32> @test_add_v4i32(<4 x i32> %arg1, <4 x i32> %arg2) {18 %ret = add <4 x i32> %arg1, %arg219 ret <4 x i32> %ret20 }21 22 define <2 x i64> @test_add_v2i64(<2 x i64> %arg1, <2 x i64> %arg2) {23 %ret = add <2 x i64> %arg1, %arg224 ret <2 x i64> %ret25 }26 27...28---29name: test_add_v16i830# ALL-LABEL: name: test_add_v16i831alignment: 1632legalized: true33regBankSelected: true34# NOVL: registers:35# NOVL-NEXT: - { id: 0, class: vr128, preferred-register: '', flags: [ ] }36# NOVL-NEXT: - { id: 1, class: vr128, preferred-register: '', flags: [ ] }37# NOVL-NEXT: - { id: 2, class: vr128, preferred-register: '', flags: [ ] }38#39# AVX512VL: registers:40# AVX512VL-NEXT: - { id: 0, class: vr128, preferred-register: '', flags: [ ] }41# AVX512VL-NEXT: - { id: 1, class: vr128, preferred-register: '', flags: [ ] }42# AVX512VL-NEXT: - { id: 2, class: vr128, preferred-register: '', flags: [ ] }43#44# AVX512BWVL: registers:45# AVX512BWVL-NEXT: - { id: 0, class: vr128x, preferred-register: '', flags: [ ] }46# AVX512BWVL-NEXT: - { id: 1, class: vr128x, preferred-register: '', flags: [ ] }47# AVX512BWVL-NEXT: - { id: 2, class: vr128x, preferred-register: '', flags: [ ] }48registers:49 - { id: 0, class: vecr }50 - { id: 1, class: vecr }51 - { id: 2, class: vecr }52# SSE2: %2:vr128 = PADDBrr %0, %153#54# AVX1: %2:vr128 = VPADDBrr %0, %155#56# AVX512VL: %2:vr128 = VPADDBrr %0, %157#58# AVX512BWVL: %2:vr128x = VPADDBZ128rr %0, %159body: |60 bb.1 (%ir-block.0):61 liveins: $xmm0, $xmm162 63 %0(<16 x s8>) = COPY $xmm064 %1(<16 x s8>) = COPY $xmm165 %2(<16 x s8>) = G_ADD %0, %166 $xmm0 = COPY %2(<16 x s8>)67 RET 0, implicit $xmm068 69...70---71name: test_add_v8i1672# ALL-LABEL: name: test_add_v8i1673alignment: 1674legalized: true75regBankSelected: true76# NOVL: registers:77# NOVL-NEXT: - { id: 0, class: vr128, preferred-register: '', flags: [ ] }78# NOVL-NEXT: - { id: 1, class: vr128, preferred-register: '', flags: [ ] }79# NOVL-NEXT: - { id: 2, class: vr128, preferred-register: '', flags: [ ] }80#81# AVX512VL: registers:82# AVX512VL-NEXT: - { id: 0, class: vr128, preferred-register: '', flags: [ ] }83# AVX512VL-NEXT: - { id: 1, class: vr128, preferred-register: '', flags: [ ] }84# AVX512VL-NEXT: - { id: 2, class: vr128, preferred-register: '', flags: [ ] }85#86# AVX512BWVL: registers:87# AVX512BWVL-NEXT: - { id: 0, class: vr128x, preferred-register: '', flags: [ ] }88# AVX512BWVL-NEXT: - { id: 1, class: vr128x, preferred-register: '', flags: [ ] }89# AVX512BWVL-NEXT: - { id: 2, class: vr128x, preferred-register: '', flags: [ ] }90registers:91 - { id: 0, class: vecr }92 - { id: 1, class: vecr }93 - { id: 2, class: vecr }94# SSE2: %2:vr128 = PADDWrr %0, %195#96# AVX1: %2:vr128 = VPADDWrr %0, %197#98# AVX512VL: %2:vr128 = VPADDWrr %0, %199#100# AVX512BWVL: %2:vr128x = VPADDWZ128rr %0, %1101body: |102 bb.1 (%ir-block.0):103 liveins: $xmm0, $xmm1104 105 %0(<8 x s16>) = COPY $xmm0106 %1(<8 x s16>) = COPY $xmm1107 %2(<8 x s16>) = G_ADD %0, %1108 $xmm0 = COPY %2(<8 x s16>)109 RET 0, implicit $xmm0110 111...112---113name: test_add_v4i32114# ALL-LABEL: name: test_add_v4i32115alignment: 16116legalized: true117regBankSelected: true118# NOVL: registers:119# NOVL-NEXT: - { id: 0, class: vr128, preferred-register: '', flags: [ ] }120# NOVL-NEXT: - { id: 1, class: vr128, preferred-register: '', flags: [ ] }121# NOVL-NEXT: - { id: 2, class: vr128, preferred-register: '', flags: [ ] }122#123# AVX512VL: registers:124# AVX512VL-NEXT: - { id: 0, class: vr128x, preferred-register: '', flags: [ ] }125# AVX512VL-NEXT: - { id: 1, class: vr128x, preferred-register: '', flags: [ ] }126# AVX512VL-NEXT: - { id: 2, class: vr128x, preferred-register: '', flags: [ ] }127#128# AVX512BWVL: registers:129# AVX512BWVL-NEXT: - { id: 0, class: vr128x, preferred-register: '', flags: [ ] }130# AVX512BWVL-NEXT: - { id: 1, class: vr128x, preferred-register: '', flags: [ ] }131# AVX512BWVL-NEXT: - { id: 2, class: vr128x, preferred-register: '', flags: [ ] }132registers:133 - { id: 0, class: vecr }134 - { id: 1, class: vecr }135 - { id: 2, class: vecr }136# SSE2: %2:vr128 = PADDDrr %0, %1137#138# AVX1: %2:vr128 = VPADDDrr %0, %1139#140# AVX512VL: %2:vr128x = VPADDDZ128rr %0, %1141#142# AVX512BWVL: %2:vr128x = VPADDDZ128rr %0, %1143body: |144 bb.1 (%ir-block.0):145 liveins: $xmm0, $xmm1146 147 %0(<4 x s32>) = COPY $xmm0148 %1(<4 x s32>) = COPY $xmm1149 %2(<4 x s32>) = G_ADD %0, %1150 $xmm0 = COPY %2(<4 x s32>)151 RET 0, implicit $xmm0152 153...154---155name: test_add_v2i64156# ALL-LABEL: name: test_add_v2i64157alignment: 16158legalized: true159regBankSelected: true160# NOVL: registers:161# NOVL-NEXT: - { id: 0, class: vr128, preferred-register: '', flags: [ ] }162# NOVL-NEXT: - { id: 1, class: vr128, preferred-register: '', flags: [ ] }163# NOVL-NEXT: - { id: 2, class: vr128, preferred-register: '', flags: [ ] }164#165# AVX512VL: registers:166# AVX512VL-NEXT: - { id: 0, class: vr128x, preferred-register: '', flags: [ ] }167# AVX512VL-NEXT: - { id: 1, class: vr128x, preferred-register: '', flags: [ ] }168# AVX512VL-NEXT: - { id: 2, class: vr128x, preferred-register: '', flags: [ ] }169#170# AVX512BWVL: registers:171# AVX512BWVL-NEXT: - { id: 0, class: vr128x, preferred-register: '', flags: [ ] }172# AVX512BWVL-NEXT: - { id: 1, class: vr128x, preferred-register: '', flags: [ ] }173# AVX512BWVL-NEXT: - { id: 2, class: vr128x, preferred-register: '', flags: [ ] }174registers:175 - { id: 0, class: vecr }176 - { id: 1, class: vecr }177 - { id: 2, class: vecr }178# SSE2: %2:vr128 = PADDQrr %0, %1179#180# AVX1: %2:vr128 = VPADDQrr %0, %1181#182# AVX512VL: %2:vr128x = VPADDQZ128rr %0, %1183#184# AVX512BWVL: %2:vr128x = VPADDQZ128rr %0, %1185body: |186 bb.1 (%ir-block.0):187 liveins: $xmm0, $xmm1188 189 %0(<2 x s64>) = COPY $xmm0190 %1(<2 x s64>) = COPY $xmm1191 %2(<2 x s64>) = G_ADD %0, %1192 $xmm0 = COPY %2(<2 x s64>)193 RET 0, implicit $xmm0194 195...196