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1# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=AVX22# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f,+avx512vl -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=AVX512VL3# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f,+avx512vl,+avx512bw -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=AVX512BWVL4 5--- |6 define <32 x i8> @test_add_v32i8(<32 x i8> %arg1, <32 x i8> %arg2) {7 %ret = add <32 x i8> %arg1, %arg28 ret <32 x i8> %ret9 }10 11 define <16 x i16> @test_add_v16i16(<16 x i16> %arg1, <16 x i16> %arg2) {12 %ret = add <16 x i16> %arg1, %arg213 ret <16 x i16> %ret14 }15 16 define <8 x i32> @test_add_v8i32(<8 x i32> %arg1, <8 x i32> %arg2) {17 %ret = add <8 x i32> %arg1, %arg218 ret <8 x i32> %ret19 }20 21 define <4 x i64> @test_add_v4i64(<4 x i64> %arg1, <4 x i64> %arg2) {22 %ret = add <4 x i64> %arg1, %arg223 ret <4 x i64> %ret24 }25...26---27name: test_add_v32i828# ALL-LABEL: name: test_add_v32i829alignment: 1630legalized: true31regBankSelected: true32# AVX2: registers:33# AVX2-NEXT: - { id: 0, class: vr256, preferred-register: '', flags: [ ] }34# AVX2-NEXT: - { id: 1, class: vr256, preferred-register: '', flags: [ ] }35# AVX2-NEXT: - { id: 2, class: vr256, preferred-register: '', flags: [ ] }36#37# AVX512VL: registers:38# AVX512VL-NEXT: - { id: 0, class: vr256, preferred-register: '', flags: [ ] }39# AVX512VL-NEXT: - { id: 1, class: vr256, preferred-register: '', flags: [ ] }40# AVX512VL-NEXT: - { id: 2, class: vr256, preferred-register: '', flags: [ ] }41#42# AVX512BWVL: registers:43# AVX512BWVL-NEXT: - { id: 0, class: vr256x, preferred-register: '', flags: [ ] }44# AVX512BWVL-NEXT: - { id: 1, class: vr256x, preferred-register: '', flags: [ ] }45# AVX512BWVL-NEXT: - { id: 2, class: vr256x, preferred-register: '', flags: [ ] }46registers:47 - { id: 0, class: vecr }48 - { id: 1, class: vecr }49 - { id: 2, class: vecr }50# AVX2: %2:vr256 = VPADDBYrr %0, %151#52# AVX512VL: %2:vr256 = VPADDBYrr %0, %153#54# AVX512BWVL: %2:vr256x = VPADDBZ256rr %0, %155body: |56 bb.1 (%ir-block.0):57 liveins: $ymm0, $ymm158 59 %0(<32 x s8>) = COPY $ymm060 %1(<32 x s8>) = COPY $ymm161 %2(<32 x s8>) = G_ADD %0, %162 $ymm0 = COPY %2(<32 x s8>)63 RET 0, implicit $ymm064 65...66---67name: test_add_v16i1668# ALL-LABEL: name: test_add_v16i1669alignment: 1670legalized: true71regBankSelected: true72# AVX2: registers:73# AVX2-NEXT: - { id: 0, class: vr256, preferred-register: '', flags: [ ] }74# AVX2-NEXT: - { id: 1, class: vr256, preferred-register: '', flags: [ ] }75# AVX2-NEXT: - { id: 2, class: vr256, preferred-register: '', flags: [ ] }76#77# AVX512VL: registers:78# AVX512VL-NEXT: - { id: 0, class: vr256, preferred-register: '', flags: [ ] }79# AVX512VL-NEXT: - { id: 1, class: vr256, preferred-register: '', flags: [ ] }80# AVX512VL-NEXT: - { id: 2, class: vr256, preferred-register: '', flags: [ ] }81#82# AVX512BWVL: registers:83# AVX512BWVL-NEXT: - { id: 0, class: vr256x, preferred-register: '', flags: [ ] }84# AVX512BWVL-NEXT: - { id: 1, class: vr256x, preferred-register: '', flags: [ ] }85# AVX512BWVL-NEXT: - { id: 2, class: vr256x, preferred-register: '', flags: [ ] }86registers:87 - { id: 0, class: vecr }88 - { id: 1, class: vecr }89 - { id: 2, class: vecr }90# AVX2: %2:vr256 = VPADDWYrr %0, %191#92# AVX512VL: %2:vr256 = VPADDWYrr %0, %193#94# AVX512BWVL: %2:vr256x = VPADDWZ256rr %0, %195body: |96 bb.1 (%ir-block.0):97 liveins: $ymm0, $ymm198 99 %0(<16 x s16>) = COPY $ymm0100 %1(<16 x s16>) = COPY $ymm1101 %2(<16 x s16>) = G_ADD %0, %1102 $ymm0 = COPY %2(<16 x s16>)103 RET 0, implicit $ymm0104 105...106---107name: test_add_v8i32108# ALL-LABEL: name: test_add_v8i32109alignment: 16110legalized: true111regBankSelected: true112# AVX2: registers:113# AVX2-NEXT: - { id: 0, class: vr256, preferred-register: '', flags: [ ] }114# AVX2-NEXT: - { id: 1, class: vr256, preferred-register: '', flags: [ ] }115# AVX2-NEXT: - { id: 2, class: vr256, preferred-register: '', flags: [ ] }116#117# AVX512VL: registers:118# AVX512VL-NEXT: - { id: 0, class: vr256x, preferred-register: '', flags: [ ] }119# AVX512VL-NEXT: - { id: 1, class: vr256x, preferred-register: '', flags: [ ] }120# AVX512VL-NEXT: - { id: 2, class: vr256x, preferred-register: '', flags: [ ] }121#122# AVX512BWVL: registers:123# AVX512BWVL-NEXT: - { id: 0, class: vr256x, preferred-register: '', flags: [ ] }124# AVX512BWVL-NEXT: - { id: 1, class: vr256x, preferred-register: '', flags: [ ] }125# AVX512BWVL-NEXT: - { id: 2, class: vr256x, preferred-register: '', flags: [ ] }126registers:127 - { id: 0, class: vecr }128 - { id: 1, class: vecr }129 - { id: 2, class: vecr }130# AVX2: %2:vr256 = VPADDDYrr %0, %1131#132# AVX512VL: %2:vr256x = VPADDDZ256rr %0, %1133#134# AVX512BWVL: %2:vr256x = VPADDDZ256rr %0, %1135body: |136 bb.1 (%ir-block.0):137 liveins: $ymm0, $ymm1138 139 %0(<8 x s32>) = COPY $ymm0140 %1(<8 x s32>) = COPY $ymm1141 %2(<8 x s32>) = G_ADD %0, %1142 $ymm0 = COPY %2(<8 x s32>)143 RET 0, implicit $ymm0144 145...146---147name: test_add_v4i64148# ALL-LABEL: name: test_add_v4i64149alignment: 16150legalized: true151regBankSelected: true152# AVX2: registers:153# AVX2-NEXT: - { id: 0, class: vr256, preferred-register: '', flags: [ ] }154# AVX2-NEXT: - { id: 1, class: vr256, preferred-register: '', flags: [ ] }155# AVX2-NEXT: - { id: 2, class: vr256, preferred-register: '', flags: [ ] }156#157# AVX512VL: registers:158# AVX512VL-NEXT: - { id: 0, class: vr256x, preferred-register: '', flags: [ ] }159# AVX512VL-NEXT: - { id: 1, class: vr256x, preferred-register: '', flags: [ ] }160# AVX512VL-NEXT: - { id: 2, class: vr256x, preferred-register: '', flags: [ ] }161#162# AVX512BWVL: registers:163# AVX512BWVL-NEXT: - { id: 0, class: vr256x, preferred-register: '', flags: [ ] }164# AVX512BWVL-NEXT: - { id: 1, class: vr256x, preferred-register: '', flags: [ ] }165# AVX512BWVL-NEXT: - { id: 2, class: vr256x, preferred-register: '', flags: [ ] }166registers:167 - { id: 0, class: vecr }168 - { id: 1, class: vecr }169 - { id: 2, class: vecr }170# AVX2: %2:vr256 = VPADDQYrr %0, %1171#172# AVX512VL: %2:vr256x = VPADDQZ256rr %0, %1173#174# AVX512BWVL: %2:vr256x = VPADDQZ256rr %0, %1175body: |176 bb.1 (%ir-block.0):177 liveins: $ymm0, $ymm1178 179 %0(<4 x s64>) = COPY $ymm0180 %1(<4 x s64>) = COPY $ymm1181 %2(<4 x s64>) = G_ADD %0, %1182 $ymm0 = COPY %2(<4 x s64>)183 RET 0, implicit $ymm0184 185...186