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1# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=ALL,NO_AVX512VL,SSE2# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=ALL,NO_AVX512VL,AVX3# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=ALL,NO_AVX512VL,AVX512F4# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -mattr=+avx512vl -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=ALL,AVX512VL5 6--- |7 define i64 @test_add_i64(i64 %arg1, i64 %arg2) {8 %ret = add i64 %arg1, %arg29 ret i64 %ret10 }11 12 define i32 @test_add_i32(i32 %arg1, i32 %arg2) {13 %ret = add i32 %arg1, %arg214 ret i32 %ret15 }16 17 define i16 @test_add_i16(i16 %arg1, i16 %arg2) {18 %ret = add i16 %arg1, %arg219 ret i16 %ret20 }21 22 define i8 @test_add_i8(i8 %arg1, i8 %arg2) {23 %ret = add i8 %arg1, %arg224 ret i8 %ret25 }26 27 define <4 x i32> @test_add_v4i32(<4 x i32> %arg1, <4 x i32> %arg2) {28 %ret = add <4 x i32> %arg1, %arg229 ret <4 x i32> %ret30 }31 32 define <4 x float> @test_add_v4f32(<4 x float> %arg1, <4 x float> %arg2) {33 %ret = fadd <4 x float> %arg1, %arg234 ret <4 x float> %ret35 }36...37 38---39name: test_add_i6440# ALL-LABEL: name: test_add_i6441legalized: true42regBankSelected: true43registers:44 - { id: 0, class: gpr }45 - { id: 1, class: gpr }46 - { id: 2, class: gpr }47# ALL: %0:gr64 = COPY $rdi48# ALL-NEXT: %1:gr64 = COPY $rsi49# ALL-NEXT: %2:gr64 = ADD64rr %0, %150body: |51 bb.1 (%ir-block.0):52 liveins: $edi, $esi53 54 %0(s64) = COPY $rdi55 %1(s64) = COPY $rsi56 %2(s64) = G_ADD %0, %157 $rax = COPY %2(s64)58 59...60 61---62name: test_add_i3263# ALL-LABEL: name: test_add_i3264legalized: true65regBankSelected: true66registers:67 - { id: 0, class: gpr }68 - { id: 1, class: gpr }69 - { id: 2, class: gpr }70# ALL: %0:gr32 = COPY $edi71# ALL-NEXT: %1:gr32 = COPY $esi72# ALL-NEXT: %2:gr32 = ADD32rr %0, %173body: |74 bb.1 (%ir-block.0):75 liveins: $edi, $esi76 77 %0(s32) = COPY $edi78 %1(s32) = COPY $esi79 %2(s32) = G_ADD %0, %180 $eax = COPY %2(s32)81 82...83---84name: test_add_i1685# ALL-LABEL: name: test_add_i1686alignment: 1687legalized: true88regBankSelected: true89selected: false90registers:91 - { id: 0, class: gpr }92 - { id: 1, class: gpr }93 - { id: 2, class: gpr }94# ALL: %0:gr16 = COPY $di95# ALL: %1:gr16 = COPY $si96# ALL: %2:gr16 = ADD16rr %0, %1, implicit-def dead $eflags97body: |98 bb.1 (%ir-block.0):99 liveins: $edi, $esi100 101 %0(s16) = COPY $di102 %1(s16) = COPY $si103 %2(s16) = G_ADD %0, %1104 $ax = COPY %2(s16)105 RET 0, implicit $ax106 107...108---109name: test_add_i8110# ALL-LABEL: name: test_add_i8111alignment: 16112legalized: true113regBankSelected: true114selected: false115registers:116 - { id: 0, class: gpr }117 - { id: 1, class: gpr }118 - { id: 2, class: gpr }119# ALL: %0:gr8 = COPY $dil120# ALL: %1:gr8 = COPY $sil121# ALL: %2:gr8 = ADD8rr %0, %1, implicit-def dead $eflags122body: |123 bb.1 (%ir-block.0):124 liveins: $edi, $esi125 126 %0(s8) = COPY $dil127 %1(s8) = COPY $sil128 %2(s8) = G_ADD %0, %1129 $al = COPY %2(s8)130 RET 0, implicit $al131 132...133---134name: test_add_v4i32135# ALL-LABEL: name: test_add_v4i32136alignment: 16137legalized: true138regBankSelected: true139selected: false140tracksRegLiveness: true141registers:142 - { id: 0, class: vecr }143 - { id: 1, class: vecr }144 - { id: 2, class: vecr }145# NO_AVX512VL: %0:vr128 = COPY $xmm0146# NO_AVX512VL: %1:vr128 = COPY $xmm1147# SSE-NEXT: %2:vr128 = PADDDrr %0, %1148# AVX-NEXT: %2:vr128 = VPADDDrr %0, %1149# AVX512F-NEXT: %2:vr128 = VPADDDrr %0, %1150# AVX512VL: %0:vr128x = COPY $xmm0151# AVX512VL: %1:vr128x = COPY $xmm1152# AVX512VL-NEXT: %2:vr128x = VPADDDZ128rr %0, %1153body: |154 bb.1 (%ir-block.0):155 liveins: $xmm0, $xmm1156 157 %0(<4 x s32>) = COPY $xmm0158 %1(<4 x s32>) = COPY $xmm1159 %2(<4 x s32>) = G_ADD %0, %1160 $xmm0 = COPY %2(<4 x s32>)161 RET 0, implicit $xmm0162 163...164---165name: test_add_v4f32166# ALL-LABEL: name: test_add_v4f32167alignment: 16168legalized: true169regBankSelected: true170selected: false171tracksRegLiveness: true172registers:173 - { id: 0, class: vecr }174 - { id: 1, class: vecr }175 - { id: 2, class: vecr }176# SSE: %0:vr128 = COPY $xmm0177# SSE-NEXT: %1:vr128 = COPY $xmm1178# SSE-NEXT: %2:vr128 = nofpexcept ADDPSrr %0, %1179# AVX: %0:vr128 = COPY $xmm0180# AVX-NEXT: %1:vr128 = COPY $xmm1181# AVX-NEXT: %2:vr128 = nofpexcept VADDPSrr %0, %1182# AVX512F: %0:vr128 = COPY $xmm0183# AVX512F-NEXT: 1:vr128 = COPY $xmm1184# AVX512F-NEXT: %2:vr128 = nofpexcept VADDPSrr %0, %1185# AVX512VL: %0:vr128x = COPY $xmm0186# AVX512VL-NEXT: %1:vr128x = COPY $xmm1187# AVX512VL-NEXT: %2:vr128x = nofpexcept VADDPSZ128rr %0, %1188body: |189 bb.1 (%ir-block.0):190 liveins: $xmm0, $xmm1191 192 %0(<4 x s32>) = COPY $xmm0193 %1(<4 x s32>) = COPY $xmm1194 %2(<4 x s32>) = G_FADD %0, %1195 $xmm0 = COPY %2(<4 x s32>)196 RET 0, implicit $xmm0197 198...199