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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+bmi -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s3#4# Test that rules where multiple operands must be the same operand successfully5# match. Also test that the rules do not match when they're not the same6# operand.7 8---9name: test_blsr32rr10alignment: 1611legalized: true12regBankSelected: true13registers:14 - { id: 0, class: gpr }15 - { id: 1, class: gpr }16 - { id: 2, class: gpr }17 - { id: 3, class: gpr }18# G_ADD and G_AND both use %0 so we should match this.19body: |20 bb.1:21 liveins: $edi22 23 ; CHECK-LABEL: name: test_blsr32rr24 ; CHECK: liveins: $edi25 ; CHECK-NEXT: {{ $}}26 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi27 ; CHECK-NEXT: [[DEC32r:%[0-9]+]]:gr32 = DEC32r [[COPY]], implicit-def dead $eflags28 ; CHECK-NEXT: [[AND32rr:%[0-9]+]]:gr32 = AND32rr [[DEC32r]], [[COPY]], implicit-def dead $eflags29 ; CHECK-NEXT: $edi = COPY [[AND32rr]]30 %0(s32) = COPY $edi31 %1(s32) = G_CONSTANT i32 -132 %2(s32) = G_ADD %0, %133 %3(s32) = G_AND %2, %034 $edi = COPY %335 36...37---38name: test_blsr32rr_nomatch39alignment: 1640legalized: true41regBankSelected: true42registers:43 - { id: 0, class: gpr }44 - { id: 1, class: gpr }45 - { id: 2, class: gpr }46 - { id: 3, class: gpr }47# G_ADD and G_AND use different operands so we shouldn't match this.48body: |49 bb.1:50 liveins: $edi51 52 ; CHECK-LABEL: name: test_blsr32rr_nomatch53 ; CHECK: liveins: $edi54 ; CHECK-NEXT: {{ $}}55 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi56 ; CHECK-NEXT: [[MOV32ri:%[0-9]+]]:gr32 = MOV32ri -157 ; CHECK-NEXT: [[DEC32r:%[0-9]+]]:gr32 = DEC32r [[MOV32ri]], implicit-def dead $eflags58 ; CHECK-NEXT: [[AND32rr:%[0-9]+]]:gr32 = AND32rr [[DEC32r]], [[COPY]], implicit-def dead $eflags59 ; CHECK-NEXT: $edi = COPY [[AND32rr]]60 %0(s32) = COPY $edi61 %1(s32) = G_CONSTANT i32 -162 %2(s32) = G_ADD %1, %163 %3(s32) = G_AND %2, %064 $edi = COPY %365...66