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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK3 4--- |5 define i32 @test_icmp_eq_i8(i8 %a, i8 %b) {6 %r = icmp eq i8 %a, %b7 %res = zext i1 %r to i328 ret i32 %res9 }10 11 define i32 @test_icmp_eq_i16(i16 %a, i16 %b) {12 %r = icmp eq i16 %a, %b13 %res = zext i1 %r to i3214 ret i32 %res15 }16 17 define i32 @test_icmp_eq_i64(i64 %a, i64 %b) {18 %r = icmp eq i64 %a, %b19 %res = zext i1 %r to i3220 ret i32 %res21 }22 23 define i32 @test_icmp_eq_i32(i32 %a, i32 %b) {24 %r = icmp eq i32 %a, %b25 %res = zext i1 %r to i3226 ret i32 %res27 }28 29 define i32 @test_icmp_ne_i32(i32 %a, i32 %b) {30 %r = icmp ne i32 %a, %b31 %res = zext i1 %r to i3232 ret i32 %res33 }34 35 define i32 @test_icmp_ugt_i32(i32 %a, i32 %b) {36 %r = icmp ugt i32 %a, %b37 %res = zext i1 %r to i3238 ret i32 %res39 }40 41 define i32 @test_icmp_uge_i32(i32 %a, i32 %b) {42 %r = icmp uge i32 %a, %b43 %res = zext i1 %r to i3244 ret i32 %res45 }46 47 define i32 @test_icmp_ult_i32(i32 %a, i32 %b) {48 %r = icmp ult i32 %a, %b49 %res = zext i1 %r to i3250 ret i32 %res51 }52 53 define i32 @test_icmp_ule_i32(i32 %a, i32 %b) {54 %r = icmp ule i32 %a, %b55 %res = zext i1 %r to i3256 ret i32 %res57 }58 59 define i32 @test_icmp_sgt_i32(i32 %a, i32 %b) {60 %r = icmp sgt i32 %a, %b61 %res = zext i1 %r to i3262 ret i32 %res63 }64 65 define i32 @test_icmp_sge_i32(i32 %a, i32 %b) {66 %r = icmp sge i32 %a, %b67 %res = zext i1 %r to i3268 ret i32 %res69 }70 71 define i32 @test_icmp_slt_i32(i32 %a, i32 %b) {72 %r = icmp slt i32 %a, %b73 %res = zext i1 %r to i3274 ret i32 %res75 }76 77 define i32 @test_icmp_sle_i32(i32 %a, i32 %b) {78 %r = icmp sle i32 %a, %b79 %res = zext i1 %r to i3280 ret i32 %res81 }82 83...84---85name: test_icmp_eq_i886alignment: 1687legalized: true88regBankSelected: true89registers:90 - { id: 0, class: gpr }91 - { id: 1, class: gpr }92 - { id: 2, class: _ }93 - { id: 3, class: gpr }94 - { id: 4, class: gpr }95 - { id: 5, class: gpr }96 - { id: 6, class: gpr }97body: |98 bb.1 (%ir-block.0):99 liveins: $edi, $esi100 101 ; CHECK-LABEL: name: test_icmp_eq_i8102 ; CHECK: liveins: $edi, $esi103 ; CHECK-NEXT: {{ $}}104 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr8 = COPY $dil105 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr8 = COPY $sil106 ; CHECK-NEXT: CMP8rr [[COPY]], [[COPY1]], implicit-def $eflags107 ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags108 ; CHECK-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]]109 ; CHECK-NEXT: [[AND32ri:%[0-9]+]]:gr32 = AND32ri [[MOVZX32rr8_]], 1, implicit-def dead $eflags110 ; CHECK-NEXT: $eax = COPY [[AND32ri]]111 ; CHECK-NEXT: RET 0, implicit $eax112 %0(s8) = COPY $dil113 %1(s8) = COPY $sil114 %4(s8) = G_ICMP intpred(eq), %0(s8), %1115 %5(s32) = G_CONSTANT i32 1116 %6(s32) = G_ANYEXT %4(s8)117 %3(s32) = G_AND %6, %5118 $eax = COPY %3(s32)119 RET 0, implicit $eax120 121...122---123name: test_icmp_eq_i16124alignment: 16125legalized: true126regBankSelected: true127registers:128 - { id: 0, class: gpr }129 - { id: 1, class: gpr }130 - { id: 2, class: _ }131 - { id: 3, class: gpr }132 - { id: 4, class: gpr }133 - { id: 5, class: gpr }134 - { id: 6, class: gpr }135body: |136 bb.1 (%ir-block.0):137 liveins: $edi, $esi138 139 ; CHECK-LABEL: name: test_icmp_eq_i16140 ; CHECK: liveins: $edi, $esi141 ; CHECK-NEXT: {{ $}}142 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr16 = COPY $di143 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr16 = COPY $si144 ; CHECK-NEXT: CMP16rr [[COPY]], [[COPY1]], implicit-def $eflags145 ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags146 ; CHECK-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]]147 ; CHECK-NEXT: [[AND32ri:%[0-9]+]]:gr32 = AND32ri [[MOVZX32rr8_]], 1, implicit-def dead $eflags148 ; CHECK-NEXT: $eax = COPY [[AND32ri]]149 ; CHECK-NEXT: RET 0, implicit $eax150 %0(s16) = COPY $di151 %1(s16) = COPY $si152 %4(s8) = G_ICMP intpred(eq), %0(s16), %1153 %5(s32) = G_CONSTANT i32 1154 %6(s32) = G_ANYEXT %4(s8)155 %3(s32) = G_AND %6, %5156 $eax = COPY %3(s32)157 RET 0, implicit $eax158 159...160---161name: test_icmp_eq_i64162alignment: 16163legalized: true164regBankSelected: true165registers:166 - { id: 0, class: gpr }167 - { id: 1, class: gpr }168 - { id: 2, class: _ }169 - { id: 3, class: gpr }170 - { id: 4, class: gpr }171 - { id: 5, class: gpr }172 - { id: 6, class: gpr }173body: |174 bb.1 (%ir-block.0):175 liveins: $rdi, $rsi176 177 ; CHECK-LABEL: name: test_icmp_eq_i64178 ; CHECK: liveins: $rdi, $rsi179 ; CHECK-NEXT: {{ $}}180 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi181 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi182 ; CHECK-NEXT: CMP64rr [[COPY]], [[COPY1]], implicit-def $eflags183 ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags184 ; CHECK-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]]185 ; CHECK-NEXT: [[AND32ri:%[0-9]+]]:gr32 = AND32ri [[MOVZX32rr8_]], 1, implicit-def dead $eflags186 ; CHECK-NEXT: $eax = COPY [[AND32ri]]187 ; CHECK-NEXT: RET 0, implicit $eax188 %0(s64) = COPY $rdi189 %1(s64) = COPY $rsi190 %4(s8) = G_ICMP intpred(eq), %0(s64), %1191 %5(s32) = G_CONSTANT i32 1192 %6(s32) = G_ANYEXT %4(s8)193 %3(s32) = G_AND %6, %5194 $eax = COPY %3(s32)195 RET 0, implicit $eax196 197...198---199name: test_icmp_eq_i32200alignment: 16201legalized: true202regBankSelected: true203registers:204 - { id: 0, class: gpr }205 - { id: 1, class: gpr }206 - { id: 2, class: _ }207 - { id: 3, class: gpr }208 - { id: 4, class: gpr }209 - { id: 5, class: gpr }210 - { id: 6, class: gpr }211body: |212 bb.1 (%ir-block.0):213 liveins: $edi, $esi214 215 ; CHECK-LABEL: name: test_icmp_eq_i32216 ; CHECK: liveins: $edi, $esi217 ; CHECK-NEXT: {{ $}}218 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi219 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi220 ; CHECK-NEXT: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags221 ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags222 ; CHECK-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]]223 ; CHECK-NEXT: [[AND32ri:%[0-9]+]]:gr32 = AND32ri [[MOVZX32rr8_]], 1, implicit-def dead $eflags224 ; CHECK-NEXT: $eax = COPY [[AND32ri]]225 ; CHECK-NEXT: RET 0, implicit $eax226 %0(s32) = COPY $edi227 %1(s32) = COPY $esi228 %4(s8) = G_ICMP intpred(eq), %0(s32), %1229 %5(s32) = G_CONSTANT i32 1230 %6(s32) = G_ANYEXT %4(s8)231 %3(s32) = G_AND %6, %5232 $eax = COPY %3(s32)233 RET 0, implicit $eax234 235...236---237name: test_icmp_ne_i32238alignment: 16239legalized: true240regBankSelected: true241registers:242 - { id: 0, class: gpr }243 - { id: 1, class: gpr }244 - { id: 2, class: _ }245 - { id: 3, class: gpr }246 - { id: 4, class: gpr }247 - { id: 5, class: gpr }248 - { id: 6, class: gpr }249body: |250 bb.1 (%ir-block.0):251 liveins: $edi, $esi252 253 ; CHECK-LABEL: name: test_icmp_ne_i32254 ; CHECK: liveins: $edi, $esi255 ; CHECK-NEXT: {{ $}}256 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi257 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi258 ; CHECK-NEXT: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags259 ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 5, implicit $eflags260 ; CHECK-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]]261 ; CHECK-NEXT: [[AND32ri:%[0-9]+]]:gr32 = AND32ri [[MOVZX32rr8_]], 1, implicit-def dead $eflags262 ; CHECK-NEXT: $eax = COPY [[AND32ri]]263 ; CHECK-NEXT: RET 0, implicit $eax264 %0(s32) = COPY $edi265 %1(s32) = COPY $esi266 %4(s8) = G_ICMP intpred(ne), %0(s32), %1267 %5(s32) = G_CONSTANT i32 1268 %6(s32) = G_ANYEXT %4(s8)269 %3(s32) = G_AND %6, %5270 $eax = COPY %3(s32)271 RET 0, implicit $eax272 273...274---275name: test_icmp_ugt_i32276alignment: 16277legalized: true278regBankSelected: true279registers:280 - { id: 0, class: gpr }281 - { id: 1, class: gpr }282 - { id: 2, class: _ }283 - { id: 3, class: gpr }284 - { id: 4, class: gpr }285 - { id: 5, class: gpr }286 - { id: 6, class: gpr }287body: |288 bb.1 (%ir-block.0):289 liveins: $edi, $esi290 291 ; CHECK-LABEL: name: test_icmp_ugt_i32292 ; CHECK: liveins: $edi, $esi293 ; CHECK-NEXT: {{ $}}294 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi295 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi296 ; CHECK-NEXT: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags297 ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 7, implicit $eflags298 ; CHECK-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]]299 ; CHECK-NEXT: [[AND32ri:%[0-9]+]]:gr32 = AND32ri [[MOVZX32rr8_]], 1, implicit-def dead $eflags300 ; CHECK-NEXT: $eax = COPY [[AND32ri]]301 ; CHECK-NEXT: RET 0, implicit $eax302 %0(s32) = COPY $edi303 %1(s32) = COPY $esi304 %4(s8) = G_ICMP intpred(ugt), %0(s32), %1305 %5(s32) = G_CONSTANT i32 1306 %6(s32) = G_ANYEXT %4(s8)307 %3(s32) = G_AND %6, %5308 $eax = COPY %3(s32)309 RET 0, implicit $eax310 311...312---313name: test_icmp_uge_i32314alignment: 16315legalized: true316regBankSelected: true317registers:318 - { id: 0, class: gpr }319 - { id: 1, class: gpr }320 - { id: 2, class: _ }321 - { id: 3, class: gpr }322 - { id: 4, class: gpr }323 - { id: 5, class: gpr }324 - { id: 6, class: gpr }325body: |326 bb.1 (%ir-block.0):327 liveins: $edi, $esi328 329 ; CHECK-LABEL: name: test_icmp_uge_i32330 ; CHECK: liveins: $edi, $esi331 ; CHECK-NEXT: {{ $}}332 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi333 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi334 ; CHECK-NEXT: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags335 ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 3, implicit $eflags336 ; CHECK-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]]337 ; CHECK-NEXT: [[AND32ri:%[0-9]+]]:gr32 = AND32ri [[MOVZX32rr8_]], 1, implicit-def dead $eflags338 ; CHECK-NEXT: $eax = COPY [[AND32ri]]339 ; CHECK-NEXT: RET 0, implicit $eax340 %0(s32) = COPY $edi341 %1(s32) = COPY $esi342 %4(s8) = G_ICMP intpred(uge), %0(s32), %1343 %5(s32) = G_CONSTANT i32 1344 %6(s32) = G_ANYEXT %4(s8)345 %3(s32) = G_AND %6, %5346 $eax = COPY %3(s32)347 RET 0, implicit $eax348 349...350---351name: test_icmp_ult_i32352alignment: 16353legalized: true354regBankSelected: true355registers:356 - { id: 0, class: gpr }357 - { id: 1, class: gpr }358 - { id: 2, class: _ }359 - { id: 3, class: gpr }360 - { id: 4, class: gpr }361 - { id: 5, class: gpr }362 - { id: 6, class: gpr }363body: |364 bb.1 (%ir-block.0):365 liveins: $edi, $esi366 367 ; CHECK-LABEL: name: test_icmp_ult_i32368 ; CHECK: liveins: $edi, $esi369 ; CHECK-NEXT: {{ $}}370 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi371 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi372 ; CHECK-NEXT: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags373 ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 2, implicit $eflags374 ; CHECK-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]]375 ; CHECK-NEXT: [[AND32ri:%[0-9]+]]:gr32 = AND32ri [[MOVZX32rr8_]], 1, implicit-def dead $eflags376 ; CHECK-NEXT: $eax = COPY [[AND32ri]]377 ; CHECK-NEXT: RET 0, implicit $eax378 %0(s32) = COPY $edi379 %1(s32) = COPY $esi380 %4(s8) = G_ICMP intpred(ult), %0(s32), %1381 %5(s32) = G_CONSTANT i32 1382 %6(s32) = G_ANYEXT %4(s8)383 %3(s32) = G_AND %6, %5384 $eax = COPY %3(s32)385 RET 0, implicit $eax386 387...388---389name: test_icmp_ule_i32390alignment: 16391legalized: true392regBankSelected: true393registers:394 - { id: 0, class: gpr }395 - { id: 1, class: gpr }396 - { id: 2, class: _ }397 - { id: 3, class: gpr }398 - { id: 4, class: gpr }399 - { id: 5, class: gpr }400 - { id: 6, class: gpr }401body: |402 bb.1 (%ir-block.0):403 liveins: $edi, $esi404 405 ; CHECK-LABEL: name: test_icmp_ule_i32406 ; CHECK: liveins: $edi, $esi407 ; CHECK-NEXT: {{ $}}408 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi409 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi410 ; CHECK-NEXT: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags411 ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 6, implicit $eflags412 ; CHECK-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]]413 ; CHECK-NEXT: [[AND32ri:%[0-9]+]]:gr32 = AND32ri [[MOVZX32rr8_]], 1, implicit-def dead $eflags414 ; CHECK-NEXT: $eax = COPY [[AND32ri]]415 ; CHECK-NEXT: RET 0, implicit $eax416 %0(s32) = COPY $edi417 %1(s32) = COPY $esi418 %4(s8) = G_ICMP intpred(ule), %0(s32), %1419 %5(s32) = G_CONSTANT i32 1420 %6(s32) = G_ANYEXT %4(s8)421 %3(s32) = G_AND %6, %5422 $eax = COPY %3(s32)423 RET 0, implicit $eax424 425...426---427name: test_icmp_sgt_i32428alignment: 16429legalized: true430regBankSelected: true431registers:432 - { id: 0, class: gpr }433 - { id: 1, class: gpr }434 - { id: 2, class: _ }435 - { id: 3, class: gpr }436 - { id: 4, class: gpr }437 - { id: 5, class: gpr }438 - { id: 6, class: gpr }439body: |440 bb.1 (%ir-block.0):441 liveins: $edi, $esi442 443 ; CHECK-LABEL: name: test_icmp_sgt_i32444 ; CHECK: liveins: $edi, $esi445 ; CHECK-NEXT: {{ $}}446 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi447 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi448 ; CHECK-NEXT: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags449 ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 15, implicit $eflags450 ; CHECK-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]]451 ; CHECK-NEXT: [[AND32ri:%[0-9]+]]:gr32 = AND32ri [[MOVZX32rr8_]], 1, implicit-def dead $eflags452 ; CHECK-NEXT: $eax = COPY [[AND32ri]]453 ; CHECK-NEXT: RET 0, implicit $eax454 %0(s32) = COPY $edi455 %1(s32) = COPY $esi456 %4(s8) = G_ICMP intpred(sgt), %0(s32), %1457 %5(s32) = G_CONSTANT i32 1458 %6(s32) = G_ANYEXT %4(s8)459 %3(s32) = G_AND %6, %5460 $eax = COPY %3(s32)461 RET 0, implicit $eax462 463...464---465name: test_icmp_sge_i32466alignment: 16467legalized: true468regBankSelected: true469registers:470 - { id: 0, class: gpr }471 - { id: 1, class: gpr }472 - { id: 2, class: _ }473 - { id: 3, class: gpr }474 - { id: 4, class: gpr }475 - { id: 5, class: gpr }476 - { id: 6, class: gpr }477body: |478 bb.1 (%ir-block.0):479 liveins: $edi, $esi480 481 ; CHECK-LABEL: name: test_icmp_sge_i32482 ; CHECK: liveins: $edi, $esi483 ; CHECK-NEXT: {{ $}}484 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi485 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi486 ; CHECK-NEXT: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags487 ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 13, implicit $eflags488 ; CHECK-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]]489 ; CHECK-NEXT: [[AND32ri:%[0-9]+]]:gr32 = AND32ri [[MOVZX32rr8_]], 1, implicit-def dead $eflags490 ; CHECK-NEXT: $eax = COPY [[AND32ri]]491 ; CHECK-NEXT: RET 0, implicit $eax492 %0(s32) = COPY $edi493 %1(s32) = COPY $esi494 %4(s8) = G_ICMP intpred(sge), %0(s32), %1495 %5(s32) = G_CONSTANT i32 1496 %6(s32) = G_ANYEXT %4(s8)497 %3(s32) = G_AND %6, %5498 $eax = COPY %3(s32)499 RET 0, implicit $eax500 501...502---503name: test_icmp_slt_i32504alignment: 16505legalized: true506regBankSelected: true507registers:508 - { id: 0, class: gpr }509 - { id: 1, class: gpr }510 - { id: 2, class: _ }511 - { id: 3, class: gpr }512 - { id: 4, class: gpr }513 - { id: 5, class: gpr }514 - { id: 6, class: gpr }515body: |516 bb.1 (%ir-block.0):517 liveins: $edi, $esi518 519 ; CHECK-LABEL: name: test_icmp_slt_i32520 ; CHECK: liveins: $edi, $esi521 ; CHECK-NEXT: {{ $}}522 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi523 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi524 ; CHECK-NEXT: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags525 ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 12, implicit $eflags526 ; CHECK-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]]527 ; CHECK-NEXT: [[AND32ri:%[0-9]+]]:gr32 = AND32ri [[MOVZX32rr8_]], 1, implicit-def dead $eflags528 ; CHECK-NEXT: $eax = COPY [[AND32ri]]529 ; CHECK-NEXT: RET 0, implicit $eax530 %0(s32) = COPY $edi531 %1(s32) = COPY $esi532 %4(s8) = G_ICMP intpred(slt), %0(s32), %1533 %5(s32) = G_CONSTANT i32 1534 %6(s32) = G_ANYEXT %4(s8)535 %3(s32) = G_AND %6, %5536 $eax = COPY %3(s32)537 RET 0, implicit $eax538 539...540---541name: test_icmp_sle_i32542alignment: 16543legalized: true544regBankSelected: true545registers:546 - { id: 0, class: gpr }547 - { id: 1, class: gpr }548 - { id: 2, class: _ }549 - { id: 3, class: gpr }550 - { id: 4, class: gpr }551 - { id: 5, class: gpr }552 - { id: 6, class: gpr }553body: |554 bb.1 (%ir-block.0):555 liveins: $edi, $esi556 557 ; CHECK-LABEL: name: test_icmp_sle_i32558 ; CHECK: liveins: $edi, $esi559 ; CHECK-NEXT: {{ $}}560 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi561 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi562 ; CHECK-NEXT: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags563 ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 14, implicit $eflags564 ; CHECK-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]]565 ; CHECK-NEXT: [[AND32ri:%[0-9]+]]:gr32 = AND32ri [[MOVZX32rr8_]], 1, implicit-def dead $eflags566 ; CHECK-NEXT: $eax = COPY [[AND32ri]]567 ; CHECK-NEXT: RET 0, implicit $eax568 %0(s32) = COPY $edi569 %1(s32) = COPY $esi570 %4(s8) = G_ICMP intpred(sle), %0(s32), %1571 %5(s32) = G_CONSTANT i32 1572 %6(s32) = G_ANYEXT %4(s8)573 %3(s32) = G_AND %6, %5574 $eax = COPY %3(s32)575 RET 0, implicit $eax576 577...578