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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=SSE3# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=AVX4# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=AVX512F5# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -mattr=+avx512vl -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=AVX512VL6--- |7 8 define float @test_fmul_float(float %arg1, float %arg2) {9 %ret = fmul float %arg1, %arg210 ret float %ret11 }12 13 define double @test_fmul_double(double %arg1, double %arg2) {14 %ret = fmul double %arg1, %arg215 ret double %ret16 }17 18...19---20name: test_fmul_float21alignment: 1622legalized: true23regBankSelected: true24#25registers:26 - { id: 0, class: vecr, preferred-register: '' }27 - { id: 1, class: vecr, preferred-register: '' }28 - { id: 2, class: vecr, preferred-register: '' }29 - { id: 3, class: vecr, preferred-register: '' }30 - { id: 4, class: vecr, preferred-register: '' }31 - { id: 5, class: vecr, preferred-register: '' }32liveins:33fixedStack:34stack:35constants:36#37#38body: |39 bb.1 (%ir-block.0):40 liveins: $xmm0, $xmm141 42 ; SSE-LABEL: name: test_fmul_float43 ; SSE: [[COPY:%[0-9]+]]:vr128 = COPY $xmm044 ; SSE: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]45 ; SSE: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm146 ; SSE: [[COPY3:%[0-9]+]]:fr32 = COPY [[COPY2]]47 ; SSE: %4:fr32 = nofpexcept MULSSrr [[COPY1]], [[COPY3]], implicit $mxcsr48 ; SSE: [[COPY4:%[0-9]+]]:vr128 = COPY %449 ; SSE: $xmm0 = COPY [[COPY4]]50 ; SSE: RET 0, implicit $xmm051 ; AVX-LABEL: name: test_fmul_float52 ; AVX: [[COPY:%[0-9]+]]:vr128 = COPY $xmm053 ; AVX: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]54 ; AVX: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm155 ; AVX: [[COPY3:%[0-9]+]]:fr32 = COPY [[COPY2]]56 ; AVX: %4:fr32 = nofpexcept VMULSSrr [[COPY1]], [[COPY3]], implicit $mxcsr57 ; AVX: [[COPY4:%[0-9]+]]:vr128 = COPY %458 ; AVX: $xmm0 = COPY [[COPY4]]59 ; AVX: RET 0, implicit $xmm060 ; AVX512F-LABEL: name: test_fmul_float61 ; AVX512F: [[COPY:%[0-9]+]]:vr128x = COPY $xmm062 ; AVX512F: [[COPY1:%[0-9]+]]:fr32x = COPY [[COPY]]63 ; AVX512F: [[COPY2:%[0-9]+]]:vr128x = COPY $xmm164 ; AVX512F: [[COPY3:%[0-9]+]]:fr32x = COPY [[COPY2]]65 ; AVX512F: %4:fr32x = nofpexcept VMULSSZrr [[COPY1]], [[COPY3]], implicit $mxcsr66 ; AVX512F: [[COPY4:%[0-9]+]]:vr128x = COPY %467 ; AVX512F: $xmm0 = COPY [[COPY4]]68 ; AVX512F: RET 0, implicit $xmm069 ; AVX512VL-LABEL: name: test_fmul_float70 ; AVX512VL: [[COPY:%[0-9]+]]:vr128x = COPY $xmm071 ; AVX512VL: [[COPY1:%[0-9]+]]:fr32x = COPY [[COPY]]72 ; AVX512VL: [[COPY2:%[0-9]+]]:vr128x = COPY $xmm173 ; AVX512VL: [[COPY3:%[0-9]+]]:fr32x = COPY [[COPY2]]74 ; AVX512VL: %4:fr32x = nofpexcept VMULSSZrr [[COPY1]], [[COPY3]], implicit $mxcsr75 ; AVX512VL: [[COPY4:%[0-9]+]]:vr128x = COPY %476 ; AVX512VL: $xmm0 = COPY [[COPY4]]77 ; AVX512VL: RET 0, implicit $xmm078 %2:vecr(s128) = COPY $xmm079 %0:vecr(s32) = G_TRUNC %2(s128)80 %3:vecr(s128) = COPY $xmm181 %1:vecr(s32) = G_TRUNC %3(s128)82 %4:vecr(s32) = G_FMUL %0, %183 %5:vecr(s128) = G_ANYEXT %4(s32)84 $xmm0 = COPY %5(s128)85 RET 0, implicit $xmm086 87...88---89name: test_fmul_double90alignment: 1691legalized: true92regBankSelected: true93#94registers:95 - { id: 0, class: vecr, preferred-register: '' }96 - { id: 1, class: vecr, preferred-register: '' }97 - { id: 2, class: vecr, preferred-register: '' }98 - { id: 3, class: vecr, preferred-register: '' }99 - { id: 4, class: vecr, preferred-register: '' }100 - { id: 5, class: vecr, preferred-register: '' }101liveins:102fixedStack:103stack:104constants:105#106#107body: |108 bb.1 (%ir-block.0):109 liveins: $xmm0, $xmm1110 111 ; SSE-LABEL: name: test_fmul_double112 ; SSE: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0113 ; SSE: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]114 ; SSE: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1115 ; SSE: [[COPY3:%[0-9]+]]:fr64 = COPY [[COPY2]]116 ; SSE: %4:fr64 = nofpexcept MULSDrr [[COPY1]], [[COPY3]], implicit $mxcsr117 ; SSE: [[COPY4:%[0-9]+]]:vr128 = COPY %4118 ; SSE: $xmm0 = COPY [[COPY4]]119 ; SSE: RET 0, implicit $xmm0120 ; AVX-LABEL: name: test_fmul_double121 ; AVX: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0122 ; AVX: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]123 ; AVX: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1124 ; AVX: [[COPY3:%[0-9]+]]:fr64 = COPY [[COPY2]]125 ; AVX: %4:fr64 = nofpexcept VMULSDrr [[COPY1]], [[COPY3]], implicit $mxcsr126 ; AVX: [[COPY4:%[0-9]+]]:vr128 = COPY %4127 ; AVX: $xmm0 = COPY [[COPY4]]128 ; AVX: RET 0, implicit $xmm0129 ; AVX512F-LABEL: name: test_fmul_double130 ; AVX512F: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0131 ; AVX512F: [[COPY1:%[0-9]+]]:fr64x = COPY [[COPY]]132 ; AVX512F: [[COPY2:%[0-9]+]]:vr128x = COPY $xmm1133 ; AVX512F: [[COPY3:%[0-9]+]]:fr64x = COPY [[COPY2]]134 ; AVX512F: %4:fr64x = nofpexcept VMULSDZrr [[COPY1]], [[COPY3]], implicit $mxcsr135 ; AVX512F: [[COPY4:%[0-9]+]]:vr128x = COPY %4136 ; AVX512F: $xmm0 = COPY [[COPY4]]137 ; AVX512F: RET 0, implicit $xmm0138 ; AVX512VL-LABEL: name: test_fmul_double139 ; AVX512VL: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0140 ; AVX512VL: [[COPY1:%[0-9]+]]:fr64x = COPY [[COPY]]141 ; AVX512VL: [[COPY2:%[0-9]+]]:vr128x = COPY $xmm1142 ; AVX512VL: [[COPY3:%[0-9]+]]:fr64x = COPY [[COPY2]]143 ; AVX512VL: %4:fr64x = nofpexcept VMULSDZrr [[COPY1]], [[COPY3]], implicit $mxcsr144 ; AVX512VL: [[COPY4:%[0-9]+]]:vr128x = COPY %4145 ; AVX512VL: $xmm0 = COPY [[COPY4]]146 ; AVX512VL: RET 0, implicit $xmm0147 %2:vecr(s128) = COPY $xmm0148 %0:vecr(s64) = G_TRUNC %2(s128)149 %3:vecr(s128) = COPY $xmm1150 %1:vecr(s64) = G_TRUNC %3(s128)151 %4:vecr(s64) = G_FMUL %0, %1152 %5:vecr(s128) = G_ANYEXT %4(s64)153 $xmm0 = COPY %5(s128)154 RET 0, implicit $xmm0155 156...157