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1# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=AVX2# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f,+avx512vl -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=AVX512VL3--- |4 define void @test_insert_128_idx0() {5 ret void6 }7 8 define void @test_insert_128_idx0_undef() {9 ret void10 }11 12 define void @test_insert_128_idx1() {13 ret void14 }15 16 define void @test_insert_128_idx1_undef() {17 ret void18 }19 20...21---22name: test_insert_128_idx023# ALL-LABEL: name: test_insert_128_idx024alignment: 1625legalized: true26regBankSelected: true27registers:28 - { id: 0, class: vecr }29 - { id: 1, class: vecr }30 - { id: 2, class: vecr }31# AVX: %0:vr256 = COPY $ymm032# AVX-NEXT: %1:vr128 = COPY $xmm133# AVX-NEXT: %2:vr256 = VINSERTF128rri %0, %1, 034# AVX-NEXT: $ymm0 = COPY %235# AVX-NEXT: RET 0, implicit $ymm036#37# AVX512VL: %0:vr256x = COPY $ymm038# AVX512VL-NEXT: %1:vr128x = COPY $xmm139# AVX512VL-NEXT: %2:vr256x = VINSERTF32X4Z256rri %0, %1, 040# AVX512VL-NEXT: $ymm0 = COPY %241# AVX512VL-NEXT: RET 0, implicit $ymm042body: |43 bb.1 (%ir-block.0):44 liveins: $ymm0, $ymm145 46 %0(<8 x s32>) = COPY $ymm047 %1(<4 x s32>) = COPY $xmm148 %2(<8 x s32>) = G_INSERT %0(<8 x s32>), %1(<4 x s32>), 049 $ymm0 = COPY %2(<8 x s32>)50 RET 0, implicit $ymm051 52...53---54name: test_insert_128_idx0_undef55# ALL-LABEL: name: test_insert_128_idx0_undef56alignment: 1657legalized: true58regBankSelected: true59registers:60 - { id: 0, class: vecr }61 - { id: 1, class: vecr }62 - { id: 2, class: vecr }63# AVX: %1:vr128 = COPY $xmm164# AVX-NEXT: undef %2.sub_xmm:vr256 = COPY %165# AVX-NEXT: $ymm0 = COPY %266# AVX-NEXT: RET 0, implicit $ymm067#68# AVX512VL: %1:vr128x = COPY $xmm169# AVX512VL-NEXT: undef %2.sub_xmm:vr256x = COPY %170# AVX512VL-NEXT: $ymm0 = COPY %271# AVX512VL-NEXT: RET 0, implicit $ymm072body: |73 bb.1 (%ir-block.0):74 liveins: $ymm0, $ymm175 76 %0(<8 x s32>) = IMPLICIT_DEF77 %1(<4 x s32>) = COPY $xmm178 %2(<8 x s32>) = G_INSERT %0(<8 x s32>), %1(<4 x s32>), 079 $ymm0 = COPY %2(<8 x s32>)80 RET 0, implicit $ymm081 82...83---84name: test_insert_128_idx185# ALL-LABEL: name: test_insert_128_idx186alignment: 1687legalized: true88regBankSelected: true89registers:90 - { id: 0, class: vecr }91 - { id: 1, class: vecr }92 - { id: 2, class: vecr }93# AVX: %0:vr256 = COPY $ymm094# AVX-NEXT: %1:vr128 = COPY $xmm195# AVX-NEXT: %2:vr256 = VINSERTF128rri %0, %1, 196# AVX-NEXT: $ymm0 = COPY %297# AVX-NEXT: RET 0, implicit $ymm098#99# AVX512VL: %0:vr256x = COPY $ymm0100# AVX512VL-NEXT: %1:vr128x = COPY $xmm1101# AVX512VL-NEXT: %2:vr256x = VINSERTF32X4Z256rri %0, %1, 1102# AVX512VL-NEXT: $ymm0 = COPY %2103# AVX512VL-NEXT: RET 0, implicit $ymm0104body: |105 bb.1 (%ir-block.0):106 liveins: $ymm0, $ymm1107 108 %0(<8 x s32>) = COPY $ymm0109 %1(<4 x s32>) = COPY $xmm1110 %2(<8 x s32>) = G_INSERT %0(<8 x s32>), %1(<4 x s32>), 128111 $ymm0 = COPY %2(<8 x s32>)112 RET 0, implicit $ymm0113...114---115name: test_insert_128_idx1_undef116# ALL-LABEL: name: test_insert_128_idx1_undef117alignment: 16118legalized: true119regBankSelected: true120registers:121 - { id: 0, class: vecr }122 - { id: 1, class: vecr }123 - { id: 2, class: vecr }124# AVX: %0:vr256 = IMPLICIT_DEF125# AVX-NEXT: %1:vr128 = COPY $xmm1126# AVX-NEXT: %2:vr256 = VINSERTF128rri %0, %1, 1127# AVX-NEXT: $ymm0 = COPY %2128# AVX-NEXT: RET 0, implicit $ymm0129#130# AVX512VL: %0:vr256x = IMPLICIT_DEF131# AVX512VL-NEXT: %1:vr128x = COPY $xmm1132# AVX512VL-NEXT: %2:vr256x = VINSERTF32X4Z256rri %0, %1, 1133# AVX512VL-NEXT: $ymm0 = COPY %2134# AVX512VL-NEXT: RET 0, implicit $ymm0135body: |136 bb.1 (%ir-block.0):137 liveins: $ymm0, $ymm1138 139 %0(<8 x s32>) = IMPLICIT_DEF140 %1(<4 x s32>) = COPY $xmm1141 %2(<8 x s32>) = G_INSERT %0(<8 x s32>), %1(<4 x s32>), 128142 $ymm0 = COPY %2(<8 x s32>)143 RET 0, implicit $ymm0144...145