240 lines · plain
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL3 4--- |5 define void @test_insert_128_idx0() {6 ret void7 }8 9 define void @test_insert_128_idx0_undef() {10 ret void11 }12 13 define void @test_insert_128_idx1() {14 ret void15 }16 17 define void @test_insert_128_idx1_undef() {18 ret void19 }20 21 define void @test_insert_256_idx0() {22 ret void23 }24 25 define void @test_insert_256_idx0_undef() {26 ret void27 }28 29 define void @test_insert_256_idx1() {30 ret void31 }32 33 define void @test_insert_256_idx1_undef() {34 ret void35 }36 37...38---39name: test_insert_128_idx040alignment: 1641legalized: true42regBankSelected: true43registers:44 - { id: 0, class: vecr }45 - { id: 1, class: vecr }46 - { id: 2, class: vecr }47body: |48 bb.1 (%ir-block.0):49 liveins: $zmm0, $ymm150 51 ; ALL-LABEL: name: test_insert_128_idx052 ; ALL: [[COPY:%[0-9]+]]:vr512 = COPY $zmm053 ; ALL: [[COPY1:%[0-9]+]]:vr128x = COPY $xmm154 ; ALL: [[VINSERTF32X4Zrri:%[0-9]+]]:vr512 = VINSERTF32X4Zrri [[COPY]], [[COPY1]], 055 ; ALL: $zmm0 = COPY [[VINSERTF32X4Zrri]]56 ; ALL: RET 0, implicit $ymm057 %0(<16 x s32>) = COPY $zmm058 %1(<4 x s32>) = COPY $xmm159 %2(<16 x s32>) = G_INSERT %0(<16 x s32>), %1(<4 x s32>), 060 $zmm0 = COPY %2(<16 x s32>)61 RET 0, implicit $ymm062 63...64---65name: test_insert_128_idx0_undef66alignment: 1667legalized: true68regBankSelected: true69registers:70 - { id: 0, class: vecr }71 - { id: 1, class: vecr }72 - { id: 2, class: vecr }73body: |74 bb.1 (%ir-block.0):75 liveins: $ymm0, $ymm176 77 ; ALL-LABEL: name: test_insert_128_idx0_undef78 ; ALL: [[COPY:%[0-9]+]]:vr128x = COPY $xmm179 ; ALL: undef %2.sub_xmm:vr512 = COPY [[COPY]]80 ; ALL: $zmm0 = COPY %281 ; ALL: RET 0, implicit $ymm082 %0(<16 x s32>) = IMPLICIT_DEF83 %1(<4 x s32>) = COPY $xmm184 %2(<16 x s32>) = G_INSERT %0(<16 x s32>), %1(<4 x s32>), 085 $zmm0 = COPY %2(<16 x s32>)86 RET 0, implicit $ymm087 88...89---90name: test_insert_128_idx191alignment: 1692legalized: true93regBankSelected: true94registers:95 - { id: 0, class: vecr }96 - { id: 1, class: vecr }97 - { id: 2, class: vecr }98body: |99 bb.1 (%ir-block.0):100 liveins: $ymm0, $ymm1101 102 ; ALL-LABEL: name: test_insert_128_idx1103 ; ALL: [[COPY:%[0-9]+]]:vr512 = COPY $zmm0104 ; ALL: [[COPY1:%[0-9]+]]:vr128x = COPY $xmm1105 ; ALL: [[VINSERTF32X4Zrri:%[0-9]+]]:vr512 = VINSERTF32X4Zrri [[COPY]], [[COPY1]], 1106 ; ALL: $zmm0 = COPY [[VINSERTF32X4Zrri]]107 ; ALL: RET 0, implicit $ymm0108 %0(<16 x s32>) = COPY $zmm0109 %1(<4 x s32>) = COPY $xmm1110 %2(<16 x s32>) = G_INSERT %0(<16 x s32>), %1(<4 x s32>), 128111 $zmm0 = COPY %2(<16 x s32>)112 RET 0, implicit $ymm0113...114---115name: test_insert_128_idx1_undef116alignment: 16117legalized: true118regBankSelected: true119registers:120 - { id: 0, class: vecr }121 - { id: 1, class: vecr }122 - { id: 2, class: vecr }123body: |124 bb.1 (%ir-block.0):125 liveins: $ymm0, $ymm1126 127 ; ALL-LABEL: name: test_insert_128_idx1_undef128 ; ALL: [[DEF:%[0-9]+]]:vr512 = IMPLICIT_DEF129 ; ALL: [[COPY:%[0-9]+]]:vr128x = COPY $xmm1130 ; ALL: [[VINSERTF32X4Zrri:%[0-9]+]]:vr512 = VINSERTF32X4Zrri [[DEF]], [[COPY]], 1131 ; ALL: $zmm0 = COPY [[VINSERTF32X4Zrri]]132 ; ALL: RET 0, implicit $ymm0133 %0(<16 x s32>) = IMPLICIT_DEF134 %1(<4 x s32>) = COPY $xmm1135 %2(<16 x s32>) = G_INSERT %0(<16 x s32>), %1(<4 x s32>), 128136 $zmm0 = COPY %2(<16 x s32>)137 RET 0, implicit $ymm0138...139---140name: test_insert_256_idx0141alignment: 16142legalized: true143regBankSelected: true144registers:145 - { id: 0, class: vecr }146 - { id: 1, class: vecr }147 - { id: 2, class: vecr }148body: |149 bb.1 (%ir-block.0):150 liveins: $zmm0, $ymm1151 152 ; ALL-LABEL: name: test_insert_256_idx0153 ; ALL: [[COPY:%[0-9]+]]:vr512 = COPY $zmm0154 ; ALL: [[COPY1:%[0-9]+]]:vr256x = COPY $ymm1155 ; ALL: [[VINSERTF64X4Zrri:%[0-9]+]]:vr512 = VINSERTF64X4Zrri [[COPY]], [[COPY1]], 0156 ; ALL: $zmm0 = COPY [[VINSERTF64X4Zrri]]157 ; ALL: RET 0, implicit $ymm0158 %0(<16 x s32>) = COPY $zmm0159 %1(<8 x s32>) = COPY $ymm1160 %2(<16 x s32>) = G_INSERT %0(<16 x s32>), %1(<8 x s32>), 0161 $zmm0 = COPY %2(<16 x s32>)162 RET 0, implicit $ymm0163 164...165---166name: test_insert_256_idx0_undef167alignment: 16168legalized: true169regBankSelected: true170registers:171 - { id: 0, class: vecr }172 - { id: 1, class: vecr }173 - { id: 2, class: vecr }174body: |175 bb.1 (%ir-block.0):176 liveins: $ymm0, $ymm1177 178 ; ALL-LABEL: name: test_insert_256_idx0_undef179 ; ALL: [[COPY:%[0-9]+]]:vr256x = COPY $ymm1180 ; ALL: undef %2.sub_ymm:vr512 = COPY [[COPY]]181 ; ALL: $zmm0 = COPY %2182 ; ALL: RET 0, implicit $ymm0183 %0(<16 x s32>) = IMPLICIT_DEF184 %1(<8 x s32>) = COPY $ymm1185 %2(<16 x s32>) = G_INSERT %0(<16 x s32>), %1(<8 x s32>), 0186 $zmm0 = COPY %2(<16 x s32>)187 RET 0, implicit $ymm0188 189...190---191name: test_insert_256_idx1192alignment: 16193legalized: true194regBankSelected: true195registers:196 - { id: 0, class: vecr }197 - { id: 1, class: vecr }198 - { id: 2, class: vecr }199body: |200 bb.1 (%ir-block.0):201 liveins: $ymm0, $ymm1202 203 ; ALL-LABEL: name: test_insert_256_idx1204 ; ALL: [[COPY:%[0-9]+]]:vr512 = COPY $zmm0205 ; ALL: [[COPY1:%[0-9]+]]:vr256x = COPY $ymm1206 ; ALL: [[VINSERTF64X4Zrri:%[0-9]+]]:vr512 = VINSERTF64X4Zrri [[COPY]], [[COPY1]], 1207 ; ALL: $zmm0 = COPY [[VINSERTF64X4Zrri]]208 ; ALL: RET 0, implicit $ymm0209 %0(<16 x s32>) = COPY $zmm0210 %1(<8 x s32>) = COPY $ymm1211 %2(<16 x s32>) = G_INSERT %0(<16 x s32>), %1(<8 x s32>), 256212 $zmm0 = COPY %2(<16 x s32>)213 RET 0, implicit $ymm0214...215---216name: test_insert_256_idx1_undef217alignment: 16218legalized: true219regBankSelected: true220registers:221 - { id: 0, class: vecr }222 - { id: 1, class: vecr }223 - { id: 2, class: vecr }224body: |225 bb.1 (%ir-block.0):226 liveins: $ymm0, $ymm1227 228 ; ALL-LABEL: name: test_insert_256_idx1_undef229 ; ALL: [[DEF:%[0-9]+]]:vr512 = IMPLICIT_DEF230 ; ALL: [[COPY:%[0-9]+]]:vr256x = COPY $ymm1231 ; ALL: [[VINSERTF64X4Zrri:%[0-9]+]]:vr512 = VINSERTF64X4Zrri [[DEF]], [[COPY]], 1232 ; ALL: $zmm0 = COPY [[VINSERTF64X4Zrri]]233 ; ALL: RET 0, implicit $ymm0234 %0(<16 x s32>) = IMPLICIT_DEF235 %1(<8 x s32>) = COPY $ymm1236 %2(<16 x s32>) = G_INSERT %0(<16 x s32>), %1(<8 x s32>), 256237 $zmm0 = COPY %2(<16 x s32>)238 RET 0, implicit $ymm0239...240