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1# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=ALL,NO_AVX512F,SSE2# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=ALL,NO_AVX512F,AVX3# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=ALL,AVX512F4# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -mattr=+avx512vl -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=ALL,AVX512VL5 6--- |7 define <4 x i32> @test_load_v4i32_noalign(ptr %p1) {8 %r = load <4 x i32>, ptr %p1, align 19 ret <4 x i32> %r10 }11 12 define <4 x i32> @test_load_v4i32_align(ptr %p1) {13 %r = load <4 x i32>, ptr %p1, align 1614 ret <4 x i32> %r15 }16 17 define ptr @test_store_v4i32_align(<4 x i32> %val, ptr %p1) {18 store <4 x i32> %val, ptr %p1, align 1619 ret ptr %p120 }21 22 define ptr @test_store_v4i32_noalign(<4 x i32> %val, ptr %p1) {23 store <4 x i32> %val, ptr %p1, align 124 ret ptr %p125 }26 27...28---29# ALL-LABEL: name: test_load_v4i32_noalign30name: test_load_v4i32_noalign31alignment: 1632legalized: true33regBankSelected: true34registers:35 - { id: 0, class: gpr }36 - { id: 1, class: vecr }37# ALL: %0:gr64 = COPY $rdi38# SSE: %1:vr128 = MOVUPSrm %0, 1, $noreg, 0, $noreg :: (load (<4 x s32>) from %ir.p1, align 1)39# AVX: %1:vr128 = VMOVUPSrm %0, 1, $noreg, 0, $noreg :: (load (<4 x s32>) from %ir.p1, align 1)40# AVX512F: %1:vr128 = VMOVUPSrm %0, 1, $noreg, 0, $noreg :: (load (<4 x s32>) from %ir.p1, align 1)41# AVX512VL: %1:vr128x = VMOVUPSZ128rm %0, 1, $noreg, 0, $noreg :: (load (<4 x s32>) from %ir.p1, align 1)42# ALL: $xmm0 = COPY %143body: |44 bb.1 (%ir-block.0):45 liveins: $rdi46 47 %0(p0) = COPY $rdi48 %1(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.p1, align 1)49 $xmm0 = COPY %1(<4 x s32>)50 RET 0, implicit $xmm051 52...53---54# ALL-LABEL: name: test_load_v4i32_align55name: test_load_v4i32_align56alignment: 1657legalized: true58regBankSelected: true59registers:60 - { id: 0, class: gpr }61 - { id: 1, class: vecr }62# ALL: %0:gr64 = COPY $rdi63# SSE: %1:vr128 = MOVAPSrm %0, 1, $noreg, 0, $noreg :: (load (<4 x s32>) from %ir.p1)64# AVX: %1:vr128 = VMOVAPSrm %0, 1, $noreg, 0, $noreg :: (load (<4 x s32>) from %ir.p1)65# AVX512F: %1:vr128 = VMOVAPSrm %0, 1, $noreg, 0, $noreg :: (load (<4 x s32>) from %ir.p1)66# AVX512VL: %1:vr128x = VMOVAPSZ128rm %0, 1, $noreg, 0, $noreg :: (load (<4 x s32>) from %ir.p1)67# ALL: $xmm0 = COPY %168body: |69 bb.1 (%ir-block.0):70 liveins: $rdi71 72 %0(p0) = COPY $rdi73 %1(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.p1)74 $xmm0 = COPY %1(<4 x s32>)75 RET 0, implicit $xmm076 77...78---79# ALL-LABEL: name: test_store_v4i32_align80name: test_store_v4i32_align81alignment: 1682legalized: true83regBankSelected: true84registers:85 - { id: 0, class: vecr }86 - { id: 1, class: gpr }87# NO_AVX512F: %0:vr128 = COPY $xmm088# AVX512F: %0:vr128 = COPY $xmm089# AVX512VL: %0:vr128x = COPY $xmm090# ALL: %1:gr64 = COPY $rdi91# SSE: MOVAPSmr %1, 1, $noreg, 0, $noreg, %0 :: (store (<4 x s32>) into %ir.p1)92# AVX: VMOVAPSmr %1, 1, $noreg, 0, $noreg, %0 :: (store (<4 x s32>) into %ir.p1)93# AVX512F: VMOVAPSmr %1, 1, $noreg, 0, $noreg, %0 :: (store (<4 x s32>) into %ir.p1)94# AVX512VL: VMOVAPSZ128mr %1, 1, $noreg, 0, $noreg, %0 :: (store (<4 x s32>) into %ir.p1)95# ALL: $rax = COPY %196body: |97 bb.1 (%ir-block.0):98 liveins: $rdi, $xmm099 100 %0(<4 x s32>) = COPY $xmm0101 %1(p0) = COPY $rdi102 G_STORE %0(<4 x s32>), %1(p0) :: (store (<4 x s32>) into %ir.p1, align 16)103 $rax = COPY %1(p0)104 RET 0, implicit $rax105 106...107---108# ALL-LABEL: name: test_store_v4i32_noalign109name: test_store_v4i32_noalign110alignment: 16111legalized: true112regBankSelected: true113registers:114 - { id: 0, class: vecr }115 - { id: 1, class: gpr }116# NO_AVX512F: %0:vr128 = COPY $xmm0117# AVX512F: %0:vr128 = COPY $xmm0118# AVX512VL: %0:vr128x = COPY $xmm0119# ALL: %1:gr64 = COPY $rdi120# SSE: MOVUPSmr %1, 1, $noreg, 0, $noreg, %0 :: (store (<4 x s32>) into %ir.p1, align 1)121# AVX: VMOVUPSmr %1, 1, $noreg, 0, $noreg, %0 :: (store (<4 x s32>) into %ir.p1, align 1)122# AVX512F: VMOVUPSmr %1, 1, $noreg, 0, $noreg, %0 :: (store (<4 x s32>) into %ir.p1, align 1)123# AVX512VL: VMOVUPSZ128mr %1, 1, $noreg, 0, $noreg, %0 :: (store (<4 x s32>) into %ir.p1, align 1)124# ALL: $rax = COPY %1125body: |126 bb.1 (%ir-block.0):127 liveins: $rdi, $xmm0128 129 %0(<4 x s32>) = COPY $xmm0130 %1(p0) = COPY $rdi131 G_STORE %0(<4 x s32>), %1(p0) :: (store (<4 x s32>) into %ir.p1, align 1)132 $rax = COPY %1(p0)133 RET 0, implicit $rax134 135...136