117 lines · plain
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=AVX512F3--- |4 define <16 x i32> @test_load_v16i32_noalign(ptr %p1) {5 %r = load <16 x i32>, ptr %p1, align 16 ret <16 x i32> %r7 }8 9 define <16 x i32> @test_load_v16i32_align(ptr %p1) {10 %r = load <16 x i32>, ptr %p1, align 3211 ret <16 x i32> %r12 }13 14 define void @test_store_v16i32_noalign(<16 x i32> %val, ptr %p1) {15 store <16 x i32> %val, ptr %p1, align 116 ret void17 }18 19 define void @test_store_v16i32_align(<16 x i32> %val, ptr %p1) {20 store <16 x i32> %val, ptr %p1, align 3221 ret void22 }23 24...25---26name: test_load_v16i32_noalign27alignment: 1628legalized: true29regBankSelected: true30registers:31 - { id: 0, class: gpr }32 - { id: 1, class: vecr }33body: |34 bb.1 (%ir-block.0):35 liveins: $rdi36 37 ; AVX512F-LABEL: name: test_load_v16i32_noalign38 ; AVX512F: [[COPY:%[0-9]+]]:gr64 = COPY $rdi39 ; AVX512F: [[VMOVUPSZrm:%[0-9]+]]:vr512 = VMOVUPSZrm [[COPY]], 1, $noreg, 0, $noreg :: (load (<16 x s32>) from %ir.p1, align 1)40 ; AVX512F: $zmm0 = COPY [[VMOVUPSZrm]]41 ; AVX512F: RET 0, implicit $zmm042 %0(p0) = COPY $rdi43 %1(<16 x s32>) = G_LOAD %0(p0) :: (load (<16 x s32>) from %ir.p1, align 1)44 $zmm0 = COPY %1(<16 x s32>)45 RET 0, implicit $zmm046 47...48---49name: test_load_v16i32_align50alignment: 1651legalized: true52regBankSelected: true53registers:54 - { id: 0, class: gpr }55 - { id: 1, class: vecr }56body: |57 bb.1 (%ir-block.0):58 liveins: $rdi59 60 ; AVX512F-LABEL: name: test_load_v16i32_align61 ; AVX512F: [[COPY:%[0-9]+]]:gr64 = COPY $rdi62 ; AVX512F: [[VMOVUPSZrm:%[0-9]+]]:vr512 = VMOVUPSZrm [[COPY]], 1, $noreg, 0, $noreg :: (load (<16 x s32>) from %ir.p1, align 32)63 ; AVX512F: $zmm0 = COPY [[VMOVUPSZrm]]64 ; AVX512F: RET 0, implicit $zmm065 %0(p0) = COPY $rdi66 %1(<16 x s32>) = G_LOAD %0(p0) :: (load (<16 x s32>) from %ir.p1, align 32)67 $zmm0 = COPY %1(<16 x s32>)68 RET 0, implicit $zmm069 70...71---72name: test_store_v16i32_noalign73alignment: 1674legalized: true75regBankSelected: true76registers:77 - { id: 0, class: vecr }78 - { id: 1, class: gpr }79body: |80 bb.1 (%ir-block.0):81 liveins: $rdi, $zmm082 83 ; AVX512F-LABEL: name: test_store_v16i32_noalign84 ; AVX512F: [[COPY:%[0-9]+]]:vr512 = COPY $zmm085 ; AVX512F: [[COPY1:%[0-9]+]]:gr64 = COPY $rdi86 ; AVX512F: VMOVUPSZmr [[COPY1]], 1, $noreg, 0, $noreg, [[COPY]] :: (store (<16 x s32>) into %ir.p1, align 1)87 ; AVX512F: RET 088 %0(<16 x s32>) = COPY $zmm089 %1(p0) = COPY $rdi90 G_STORE %0(<16 x s32>), %1(p0) :: (store (<16 x s32>) into %ir.p1, align 1)91 RET 092 93...94---95name: test_store_v16i32_align96alignment: 1697legalized: true98regBankSelected: true99registers:100 - { id: 0, class: vecr }101 - { id: 1, class: gpr }102body: |103 bb.1 (%ir-block.0):104 liveins: $rdi, $zmm0105 106 ; AVX512F-LABEL: name: test_store_v16i32_align107 ; AVX512F: [[COPY:%[0-9]+]]:vr512 = COPY $zmm0108 ; AVX512F: [[COPY1:%[0-9]+]]:gr64 = COPY $rdi109 ; AVX512F: VMOVUPSZmr [[COPY1]], 1, $noreg, 0, $noreg, [[COPY]] :: (store (<16 x s32>) into %ir.p1, align 32)110 ; AVX512F: RET 0111 %0(<16 x s32>) = COPY $zmm0112 %1(p0) = COPY $rdi113 G_STORE %0(<16 x s32>), %1(p0) :: (store (<16 x s32>) into %ir.p1, align 32)114 RET 0115 116...117