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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=AVX3# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f,+avx512vl -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=AVX512VL4--- |5 define void @test_merge() {6 ret void7 }8...9---10name: test_merge11#12alignment: 1613legalized: true14regBankSelected: true15#16registers:17 - { id: 0, class: vecr }18 - { id: 1, class: vecr }19#20body: |21 bb.1 (%ir-block.0):22 23 ; AVX-LABEL: name: test_merge24 ; AVX: [[DEF:%[0-9]+]]:vr128 = IMPLICIT_DEF25 ; AVX: undef %2.sub_xmm:vr256 = COPY [[DEF]]26 ; AVX: [[VINSERTF128rri:%[0-9]+]]:vr256 = VINSERTF128rri %2, [[DEF]], 127 ; AVX: $ymm0 = COPY [[VINSERTF128rri]]28 ; AVX: RET 0, implicit $ymm029 ; AVX512VL-LABEL: name: test_merge30 ; AVX512VL: [[DEF:%[0-9]+]]:vr128x = IMPLICIT_DEF31 ; AVX512VL: undef %2.sub_xmm:vr256x = COPY [[DEF]]32 ; AVX512VL: [[VINSERTF32X4Z256rri:%[0-9]+]]:vr256x = VINSERTF32X4Z256rri %2, [[DEF]], 133 ; AVX512VL: $ymm0 = COPY [[VINSERTF32X4Z256rri]]34 ; AVX512VL: RET 0, implicit $ymm035 %0(<4 x s32>) = IMPLICIT_DEF36 %1(<8 x s32>) = G_CONCAT_VECTORS %0(<4 x s32>), %0(<4 x s32>)37 $ymm0 = COPY %1(<8 x s32>)38 RET 0, implicit $ymm039 40...41 42