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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL3--- |4 define void @test_merge_v128() {5 ret void6 }7 8 define void @test_merge_v256() {9 ret void10 }11 12...13---14name: test_merge_v12815alignment: 1616legalized: true17regBankSelected: true18registers:19 - { id: 0, class: vecr }20 - { id: 1, class: vecr }21body: |22 bb.1 (%ir-block.0):23 24 ; ALL-LABEL: name: test_merge_v12825 ; ALL: [[DEF:%[0-9]+]]:vr128x = IMPLICIT_DEF26 ; ALL: undef %2.sub_xmm:vr512 = COPY [[DEF]]27 ; ALL: [[VINSERTF32X4Zrri:%[0-9]+]]:vr512 = VINSERTF32X4Zrri %2, [[DEF]], 128 ; ALL: [[VINSERTF32X4Zrri1:%[0-9]+]]:vr512 = VINSERTF32X4Zrri [[VINSERTF32X4Zrri]], [[DEF]], 229 ; ALL: [[VINSERTF32X4Zrri2:%[0-9]+]]:vr512 = VINSERTF32X4Zrri [[VINSERTF32X4Zrri1]], [[DEF]], 330 ; ALL: $zmm0 = COPY [[VINSERTF32X4Zrri2]]31 ; ALL: RET 0, implicit $zmm032 %0(<4 x s32>) = IMPLICIT_DEF33 %1(<16 x s32>) = G_CONCAT_VECTORS %0(<4 x s32>), %0(<4 x s32>), %0(<4 x s32>), %0(<4 x s32>)34 $zmm0 = COPY %1(<16 x s32>)35 RET 0, implicit $zmm036 37...38---39name: test_merge_v25640alignment: 1641legalized: true42regBankSelected: true43registers:44 - { id: 0, class: vecr }45 - { id: 1, class: vecr }46body: |47 bb.1 (%ir-block.0):48 49 ; ALL-LABEL: name: test_merge_v25650 ; ALL: [[DEF:%[0-9]+]]:vr256x = IMPLICIT_DEF51 ; ALL: undef %2.sub_ymm:vr512 = COPY [[DEF]]52 ; ALL: [[VINSERTF64X4Zrri:%[0-9]+]]:vr512 = VINSERTF64X4Zrri %2, [[DEF]], 153 ; ALL: $zmm0 = COPY [[VINSERTF64X4Zrri]]54 ; ALL: RET 0, implicit $zmm055 %0(<8 x s32>) = IMPLICIT_DEF56 %1(<16 x s32>) = G_CONCAT_VECTORS %0(<8 x s32>), %0(<8 x s32>)57 $zmm0 = COPY %1(<16 x s32>)58 RET 0, implicit $zmm059 60...61 62