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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL3 4--- |5 define i16 @test_mul_i16(i16 %arg1, i16 %arg2) {6 %ret = mul i16 %arg1, %arg27 ret i16 %ret8 }9 10 define i32 @test_mul_i32(i32 %arg1, i32 %arg2) {11 %ret = mul i32 %arg1, %arg212 ret i32 %ret13 }14 15 define i64 @test_mul_i64(i64 %arg1, i64 %arg2) {16 %ret = mul i64 %arg1, %arg217 ret i64 %ret18 }19 20...21---22name: test_mul_i1623alignment: 1624legalized: true25regBankSelected: true26registers:27 - { id: 0, class: gpr }28 - { id: 1, class: gpr }29 - { id: 2, class: gpr }30body: |31 bb.1 (%ir-block.0):32 liveins: $edi, $esi33 34 ; ALL-LABEL: name: test_mul_i1635 ; ALL: liveins: $edi, $esi36 ; ALL-NEXT: {{ $}}37 ; ALL-NEXT: [[COPY:%[0-9]+]]:gr16 = COPY $di38 ; ALL-NEXT: [[COPY1:%[0-9]+]]:gr16 = COPY $si39 ; ALL-NEXT: [[IMUL16rr:%[0-9]+]]:gr16 = IMUL16rr [[COPY]], [[COPY1]], implicit-def dead $eflags40 ; ALL-NEXT: $ax = COPY [[IMUL16rr]]41 ; ALL-NEXT: RET 0, implicit $ax42 %0(s16) = COPY $di43 %1(s16) = COPY $si44 %2(s16) = G_MUL %0, %145 $ax = COPY %2(s16)46 RET 0, implicit $ax47 48...49---50name: test_mul_i3251alignment: 1652legalized: true53regBankSelected: true54registers:55 - { id: 0, class: gpr }56 - { id: 1, class: gpr }57 - { id: 2, class: gpr }58body: |59 bb.1 (%ir-block.0):60 liveins: $edi, $esi61 62 ; ALL-LABEL: name: test_mul_i3263 ; ALL: liveins: $edi, $esi64 ; ALL-NEXT: {{ $}}65 ; ALL-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi66 ; ALL-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi67 ; ALL-NEXT: [[IMUL32rr:%[0-9]+]]:gr32 = IMUL32rr [[COPY]], [[COPY1]], implicit-def dead $eflags68 ; ALL-NEXT: $eax = COPY [[IMUL32rr]]69 ; ALL-NEXT: RET 0, implicit $eax70 %0(s32) = COPY $edi71 %1(s32) = COPY $esi72 %2(s32) = G_MUL %0, %173 $eax = COPY %2(s32)74 RET 0, implicit $eax75 76...77---78name: test_mul_i6479alignment: 1680legalized: true81regBankSelected: true82registers:83 - { id: 0, class: gpr }84 - { id: 1, class: gpr }85 - { id: 2, class: gpr }86body: |87 bb.1 (%ir-block.0):88 liveins: $rdi, $rsi89 90 ; ALL-LABEL: name: test_mul_i6491 ; ALL: liveins: $rdi, $rsi92 ; ALL-NEXT: {{ $}}93 ; ALL-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi94 ; ALL-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi95 ; ALL-NEXT: [[IMUL64rr:%[0-9]+]]:gr64 = IMUL64rr [[COPY]], [[COPY1]], implicit-def dead $eflags96 ; ALL-NEXT: $rax = COPY [[IMUL64rr]]97 ; ALL-NEXT: RET 0, implicit $rax98 %0(s64) = COPY $rdi99 %1(s64) = COPY $rsi100 %2(s64) = G_MUL %0, %1101 $rax = COPY %2(s64)102 RET 0, implicit $rax103 104...105