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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s3 4--- |5 define <8 x i16> @test_mul_v8i16(<8 x i16> %arg1, <8 x i16> %arg2) #0 {6 %ret = mul <8 x i16> %arg1, %arg27 ret <8 x i16> %ret8 }9 10 define <8 x i16> @test_mul_v8i16_avx(<8 x i16> %arg1, <8 x i16> %arg2) #1 {11 %ret = mul <8 x i16> %arg1, %arg212 ret <8 x i16> %ret13 }14 15 define <8 x i16> @test_mul_v8i16_avx512bwvl(<8 x i16> %arg1, <8 x i16> %arg2) #2 {16 %ret = mul <8 x i16> %arg1, %arg217 ret <8 x i16> %ret18 }19 20 define <4 x i32> @test_mul_v4i32(<4 x i32> %arg1, <4 x i32> %arg2) #3 {21 %ret = mul <4 x i32> %arg1, %arg222 ret <4 x i32> %ret23 }24 25 define <4 x i32> @test_mul_v4i32_avx(<4 x i32> %arg1, <4 x i32> %arg2) #1 {26 %ret = mul <4 x i32> %arg1, %arg227 ret <4 x i32> %ret28 }29 30 define <4 x i32> @test_mul_v4i32_avx512vl(<4 x i32> %arg1, <4 x i32> %arg2) #4 {31 %ret = mul <4 x i32> %arg1, %arg232 ret <4 x i32> %ret33 }34 35 define <2 x i64> @test_mul_v2i64(<2 x i64> %arg1, <2 x i64> %arg2) #5 {36 %ret = mul <2 x i64> %arg1, %arg237 ret <2 x i64> %ret38 }39 40 define <16 x i16> @test_mul_v16i16(<16 x i16> %arg1, <16 x i16> %arg2) #6 {41 %ret = mul <16 x i16> %arg1, %arg242 ret <16 x i16> %ret43 }44 45 define <16 x i16> @test_mul_v16i16_avx512bwvl(<16 x i16> %arg1, <16 x i16> %arg2) #2 {46 %ret = mul <16 x i16> %arg1, %arg247 ret <16 x i16> %ret48 }49 50 define <8 x i32> @test_mul_v8i32(<8 x i32> %arg1, <8 x i32> %arg2) #6 {51 %ret = mul <8 x i32> %arg1, %arg252 ret <8 x i32> %ret53 }54 55 define <8 x i32> @test_mul_v8i32_avx512vl(<8 x i32> %arg1, <8 x i32> %arg2) #4 {56 %ret = mul <8 x i32> %arg1, %arg257 ret <8 x i32> %ret58 }59 60 define <4 x i64> @test_mul_v4i64(<4 x i64> %arg1, <4 x i64> %arg2) #5 {61 %ret = mul <4 x i64> %arg1, %arg262 ret <4 x i64> %ret63 }64 65 define <32 x i16> @test_mul_v32i16(<32 x i16> %arg1, <32 x i16> %arg2) #7 {66 %ret = mul <32 x i16> %arg1, %arg267 ret <32 x i16> %ret68 }69 70 define <16 x i32> @test_mul_v16i32(<16 x i32> %arg1, <16 x i32> %arg2) #8 {71 %ret = mul <16 x i32> %arg1, %arg272 ret <16 x i32> %ret73 }74 75 define <8 x i64> @test_mul_v8i64(<8 x i64> %arg1, <8 x i64> %arg2) #9 {76 %ret = mul <8 x i64> %arg1, %arg277 ret <8 x i64> %ret78 }79 80 attributes #0 = { "target-features"="+sse2" }81 attributes #1 = { "target-features"="+avx" }82 attributes #2 = { "target-features"="+avx512vl,+avx512f,+avx512bw" }83 attributes #3 = { "target-features"="+sse4.1" }84 attributes #4 = { "target-features"="+avx512vl,+avx512f" }85 attributes #5 = { "target-features"="+avx2,+avx512vl,+avx512f,+avx512dq" }86 attributes #6 = { "target-features"="+avx2" }87 attributes #7 = { "target-features"="+avx512f,+avx512bw" }88 attributes #8 = { "target-features"="+avx512f" }89 attributes #9 = { "target-features"="+avx512f,+avx512dq" }90 91...92---93name: test_mul_v8i1694alignment: 1695legalized: true96regBankSelected: true97registers:98 - { id: 0, class: vecr }99 - { id: 1, class: vecr }100 - { id: 2, class: vecr }101body: |102 bb.1 (%ir-block.0):103 liveins: $xmm0, $xmm1104 105 ; CHECK-LABEL: name: test_mul_v8i16106 ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0107 ; CHECK: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm1108 ; CHECK: [[PMULLWrr:%[0-9]+]]:vr128 = PMULLWrr [[COPY]], [[COPY1]]109 ; CHECK: $xmm0 = COPY [[PMULLWrr]]110 ; CHECK: RET 0, implicit $xmm0111 %0(<8 x s16>) = COPY $xmm0112 %1(<8 x s16>) = COPY $xmm1113 %2(<8 x s16>) = G_MUL %0, %1114 $xmm0 = COPY %2(<8 x s16>)115 RET 0, implicit $xmm0116 117...118---119name: test_mul_v8i16_avx120alignment: 16121legalized: true122regBankSelected: true123registers:124 - { id: 0, class: vecr }125 - { id: 1, class: vecr }126 - { id: 2, class: vecr }127body: |128 bb.1 (%ir-block.0):129 liveins: $xmm0, $xmm1130 131 ; CHECK-LABEL: name: test_mul_v8i16_avx132 ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0133 ; CHECK: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm1134 ; CHECK: [[VPMULLWrr:%[0-9]+]]:vr128 = VPMULLWrr [[COPY]], [[COPY1]]135 ; CHECK: $xmm0 = COPY [[VPMULLWrr]]136 ; CHECK: RET 0, implicit $xmm0137 %0(<8 x s16>) = COPY $xmm0138 %1(<8 x s16>) = COPY $xmm1139 %2(<8 x s16>) = G_MUL %0, %1140 $xmm0 = COPY %2(<8 x s16>)141 RET 0, implicit $xmm0142 143...144---145name: test_mul_v8i16_avx512bwvl146alignment: 16147legalized: true148regBankSelected: true149registers:150 - { id: 0, class: vecr }151 - { id: 1, class: vecr }152 - { id: 2, class: vecr }153body: |154 bb.1 (%ir-block.0):155 liveins: $xmm0, $xmm1156 157 ; CHECK-LABEL: name: test_mul_v8i16_avx512bwvl158 ; CHECK: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0159 ; CHECK: [[COPY1:%[0-9]+]]:vr128x = COPY $xmm1160 ; CHECK: [[VPMULLWZ128rr:%[0-9]+]]:vr128x = VPMULLWZ128rr [[COPY]], [[COPY1]]161 ; CHECK: $xmm0 = COPY [[VPMULLWZ128rr]]162 ; CHECK: RET 0, implicit $xmm0163 %0(<8 x s16>) = COPY $xmm0164 %1(<8 x s16>) = COPY $xmm1165 %2(<8 x s16>) = G_MUL %0, %1166 $xmm0 = COPY %2(<8 x s16>)167 RET 0, implicit $xmm0168 169...170---171name: test_mul_v4i32172alignment: 16173legalized: true174regBankSelected: true175registers:176 - { id: 0, class: vecr }177 - { id: 1, class: vecr }178 - { id: 2, class: vecr }179body: |180 bb.1 (%ir-block.0):181 liveins: $xmm0, $xmm1182 183 ; CHECK-LABEL: name: test_mul_v4i32184 ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0185 ; CHECK: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm1186 ; CHECK: [[PMULLDrr:%[0-9]+]]:vr128 = PMULLDrr [[COPY]], [[COPY1]]187 ; CHECK: $xmm0 = COPY [[PMULLDrr]]188 ; CHECK: RET 0, implicit $xmm0189 %0(<4 x s32>) = COPY $xmm0190 %1(<4 x s32>) = COPY $xmm1191 %2(<4 x s32>) = G_MUL %0, %1192 $xmm0 = COPY %2(<4 x s32>)193 RET 0, implicit $xmm0194 195...196---197name: test_mul_v4i32_avx198alignment: 16199legalized: true200regBankSelected: true201registers:202 - { id: 0, class: vecr }203 - { id: 1, class: vecr }204 - { id: 2, class: vecr }205body: |206 bb.1 (%ir-block.0):207 liveins: $xmm0, $xmm1208 209 ; CHECK-LABEL: name: test_mul_v4i32_avx210 ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0211 ; CHECK: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm1212 ; CHECK: [[VPMULLDrr:%[0-9]+]]:vr128 = VPMULLDrr [[COPY]], [[COPY1]]213 ; CHECK: $xmm0 = COPY [[VPMULLDrr]]214 ; CHECK: RET 0, implicit $xmm0215 %0(<4 x s32>) = COPY $xmm0216 %1(<4 x s32>) = COPY $xmm1217 %2(<4 x s32>) = G_MUL %0, %1218 $xmm0 = COPY %2(<4 x s32>)219 RET 0, implicit $xmm0220 221...222---223name: test_mul_v4i32_avx512vl224alignment: 16225legalized: true226regBankSelected: true227registers:228 - { id: 0, class: vecr }229 - { id: 1, class: vecr }230 - { id: 2, class: vecr }231body: |232 bb.1 (%ir-block.0):233 liveins: $xmm0, $xmm1234 235 ; CHECK-LABEL: name: test_mul_v4i32_avx512vl236 ; CHECK: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0237 ; CHECK: [[COPY1:%[0-9]+]]:vr128x = COPY $xmm1238 ; CHECK: [[VPMULLDZ128rr:%[0-9]+]]:vr128x = VPMULLDZ128rr [[COPY]], [[COPY1]]239 ; CHECK: $xmm0 = COPY [[VPMULLDZ128rr]]240 ; CHECK: RET 0, implicit $xmm0241 %0(<4 x s32>) = COPY $xmm0242 %1(<4 x s32>) = COPY $xmm1243 %2(<4 x s32>) = G_MUL %0, %1244 $xmm0 = COPY %2(<4 x s32>)245 RET 0, implicit $xmm0246 247...248---249name: test_mul_v2i64250alignment: 16251legalized: true252regBankSelected: true253registers:254 - { id: 0, class: vecr }255 - { id: 1, class: vecr }256 - { id: 2, class: vecr }257body: |258 bb.1 (%ir-block.0):259 liveins: $xmm0, $xmm1260 261 ; CHECK-LABEL: name: test_mul_v2i64262 ; CHECK: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0263 ; CHECK: [[COPY1:%[0-9]+]]:vr128x = COPY $xmm1264 ; CHECK: [[VPMULLQZ128rr:%[0-9]+]]:vr128x = VPMULLQZ128rr [[COPY]], [[COPY1]]265 ; CHECK: $xmm0 = COPY [[VPMULLQZ128rr]]266 ; CHECK: RET 0, implicit $xmm0267 %0(<2 x s64>) = COPY $xmm0268 %1(<2 x s64>) = COPY $xmm1269 %2(<2 x s64>) = G_MUL %0, %1270 $xmm0 = COPY %2(<2 x s64>)271 RET 0, implicit $xmm0272 273...274---275name: test_mul_v16i16276alignment: 16277legalized: true278regBankSelected: true279registers:280 - { id: 0, class: vecr }281 - { id: 1, class: vecr }282 - { id: 2, class: vecr }283body: |284 bb.1 (%ir-block.0):285 liveins: $ymm0, $ymm1286 287 ; CHECK-LABEL: name: test_mul_v16i16288 ; CHECK: [[COPY:%[0-9]+]]:vr256 = COPY $ymm0289 ; CHECK: [[COPY1:%[0-9]+]]:vr256 = COPY $ymm1290 ; CHECK: [[VPMULLWYrr:%[0-9]+]]:vr256 = VPMULLWYrr [[COPY]], [[COPY1]]291 ; CHECK: $ymm0 = COPY [[VPMULLWYrr]]292 ; CHECK: RET 0, implicit $ymm0293 %0(<16 x s16>) = COPY $ymm0294 %1(<16 x s16>) = COPY $ymm1295 %2(<16 x s16>) = G_MUL %0, %1296 $ymm0 = COPY %2(<16 x s16>)297 RET 0, implicit $ymm0298 299...300---301name: test_mul_v16i16_avx512bwvl302alignment: 16303legalized: true304regBankSelected: true305registers:306 - { id: 0, class: vecr }307 - { id: 1, class: vecr }308 - { id: 2, class: vecr }309body: |310 bb.1 (%ir-block.0):311 liveins: $ymm0, $ymm1312 313 ; CHECK-LABEL: name: test_mul_v16i16_avx512bwvl314 ; CHECK: [[COPY:%[0-9]+]]:vr256x = COPY $ymm0315 ; CHECK: [[COPY1:%[0-9]+]]:vr256x = COPY $ymm1316 ; CHECK: [[VPMULLWZ256rr:%[0-9]+]]:vr256x = VPMULLWZ256rr [[COPY]], [[COPY1]]317 ; CHECK: $ymm0 = COPY [[VPMULLWZ256rr]]318 ; CHECK: RET 0, implicit $ymm0319 %0(<16 x s16>) = COPY $ymm0320 %1(<16 x s16>) = COPY $ymm1321 %2(<16 x s16>) = G_MUL %0, %1322 $ymm0 = COPY %2(<16 x s16>)323 RET 0, implicit $ymm0324 325...326---327name: test_mul_v8i32328alignment: 16329legalized: true330regBankSelected: true331registers:332 - { id: 0, class: vecr }333 - { id: 1, class: vecr }334 - { id: 2, class: vecr }335body: |336 bb.1 (%ir-block.0):337 liveins: $ymm0, $ymm1338 339 ; CHECK-LABEL: name: test_mul_v8i32340 ; CHECK: [[COPY:%[0-9]+]]:vr256 = COPY $ymm0341 ; CHECK: [[COPY1:%[0-9]+]]:vr256 = COPY $ymm1342 ; CHECK: [[VPMULLDYrr:%[0-9]+]]:vr256 = VPMULLDYrr [[COPY]], [[COPY1]]343 ; CHECK: $ymm0 = COPY [[VPMULLDYrr]]344 ; CHECK: RET 0, implicit $ymm0345 %0(<8 x s32>) = COPY $ymm0346 %1(<8 x s32>) = COPY $ymm1347 %2(<8 x s32>) = G_MUL %0, %1348 $ymm0 = COPY %2(<8 x s32>)349 RET 0, implicit $ymm0350 351...352---353name: test_mul_v8i32_avx512vl354alignment: 16355legalized: true356regBankSelected: true357registers:358 - { id: 0, class: vecr }359 - { id: 1, class: vecr }360 - { id: 2, class: vecr }361body: |362 bb.1 (%ir-block.0):363 liveins: $ymm0, $ymm1364 365 ; CHECK-LABEL: name: test_mul_v8i32_avx512vl366 ; CHECK: [[COPY:%[0-9]+]]:vr256x = COPY $ymm0367 ; CHECK: [[COPY1:%[0-9]+]]:vr256x = COPY $ymm1368 ; CHECK: [[VPMULLDZ256rr:%[0-9]+]]:vr256x = VPMULLDZ256rr [[COPY]], [[COPY1]]369 ; CHECK: $ymm0 = COPY [[VPMULLDZ256rr]]370 ; CHECK: RET 0, implicit $ymm0371 %0(<8 x s32>) = COPY $ymm0372 %1(<8 x s32>) = COPY $ymm1373 %2(<8 x s32>) = G_MUL %0, %1374 $ymm0 = COPY %2(<8 x s32>)375 RET 0, implicit $ymm0376 377...378---379name: test_mul_v4i64380alignment: 16381legalized: true382regBankSelected: true383registers:384 - { id: 0, class: vecr }385 - { id: 1, class: vecr }386 - { id: 2, class: vecr }387body: |388 bb.1 (%ir-block.0):389 liveins: $ymm0, $ymm1390 391 ; CHECK-LABEL: name: test_mul_v4i64392 ; CHECK: [[COPY:%[0-9]+]]:vr256x = COPY $ymm0393 ; CHECK: [[COPY1:%[0-9]+]]:vr256x = COPY $ymm1394 ; CHECK: [[VPMULLQZ256rr:%[0-9]+]]:vr256x = VPMULLQZ256rr [[COPY]], [[COPY1]]395 ; CHECK: $ymm0 = COPY [[VPMULLQZ256rr]]396 ; CHECK: RET 0, implicit $ymm0397 %0(<4 x s64>) = COPY $ymm0398 %1(<4 x s64>) = COPY $ymm1399 %2(<4 x s64>) = G_MUL %0, %1400 $ymm0 = COPY %2(<4 x s64>)401 RET 0, implicit $ymm0402 403...404---405name: test_mul_v32i16406alignment: 16407legalized: true408regBankSelected: true409registers:410 - { id: 0, class: vecr }411 - { id: 1, class: vecr }412 - { id: 2, class: vecr }413body: |414 bb.1 (%ir-block.0):415 liveins: $zmm0, $zmm1416 417 ; CHECK-LABEL: name: test_mul_v32i16418 ; CHECK: [[COPY:%[0-9]+]]:vr512 = COPY $zmm0419 ; CHECK: [[COPY1:%[0-9]+]]:vr512 = COPY $zmm1420 ; CHECK: [[VPMULLWZrr:%[0-9]+]]:vr512 = VPMULLWZrr [[COPY]], [[COPY1]]421 ; CHECK: $zmm0 = COPY [[VPMULLWZrr]]422 ; CHECK: RET 0, implicit $zmm0423 %0(<32 x s16>) = COPY $zmm0424 %1(<32 x s16>) = COPY $zmm1425 %2(<32 x s16>) = G_MUL %0, %1426 $zmm0 = COPY %2(<32 x s16>)427 RET 0, implicit $zmm0428 429...430---431name: test_mul_v16i32432alignment: 16433legalized: true434regBankSelected: true435registers:436 - { id: 0, class: vecr }437 - { id: 1, class: vecr }438 - { id: 2, class: vecr }439body: |440 bb.1 (%ir-block.0):441 liveins: $zmm0, $zmm1442 443 ; CHECK-LABEL: name: test_mul_v16i32444 ; CHECK: [[COPY:%[0-9]+]]:vr512 = COPY $zmm0445 ; CHECK: [[COPY1:%[0-9]+]]:vr512 = COPY $zmm1446 ; CHECK: [[VPMULLDZrr:%[0-9]+]]:vr512 = VPMULLDZrr [[COPY]], [[COPY1]]447 ; CHECK: $zmm0 = COPY [[VPMULLDZrr]]448 ; CHECK: RET 0, implicit $zmm0449 %0(<16 x s32>) = COPY $zmm0450 %1(<16 x s32>) = COPY $zmm1451 %2(<16 x s32>) = G_MUL %0, %1452 $zmm0 = COPY %2(<16 x s32>)453 RET 0, implicit $zmm0454 455...456---457name: test_mul_v8i64458alignment: 16459legalized: true460regBankSelected: true461registers:462 - { id: 0, class: vecr }463 - { id: 1, class: vecr }464 - { id: 2, class: vecr }465body: |466 bb.1 (%ir-block.0):467 liveins: $zmm0, $zmm1468 469 ; CHECK-LABEL: name: test_mul_v8i64470 ; CHECK: [[COPY:%[0-9]+]]:vr512 = COPY $zmm0471 ; CHECK: [[COPY1:%[0-9]+]]:vr512 = COPY $zmm1472 ; CHECK: [[VPMULLQZrr:%[0-9]+]]:vr512 = VPMULLQZrr [[COPY]], [[COPY1]]473 ; CHECK: $zmm0 = COPY [[VPMULLQZrr]]474 ; CHECK: RET 0, implicit $zmm0475 %0(<8 x s64>) = COPY $zmm0476 %1(<8 x s64>) = COPY $zmm1477 %2(<8 x s64>) = G_MUL %0, %1478 $zmm0 = COPY %2(<8 x s64>)479 RET 0, implicit $zmm0480 481...482