154 lines · plain
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL3 4--- |5 define i8 @test_or_i8(i8 %arg1, i8 %arg2) {6 %ret = or i8 %arg1, %arg27 ret i8 %ret8 }9 10 define i16 @test_or_i16(i16 %arg1, i16 %arg2) {11 %ret = or i16 %arg1, %arg212 ret i16 %ret13 }14 15 define i32 @test_or_i32(i32 %arg1, i32 %arg2) {16 %ret = or i32 %arg1, %arg217 ret i32 %ret18 }19 20 define i64 @test_or_i64(i64 %arg1, i64 %arg2) {21 %ret = or i64 %arg1, %arg222 ret i64 %ret23 }24 25...26---27name: test_or_i828alignment: 1629legalized: true30regBankSelected: true31registers:32 - { id: 0, class: gpr, preferred-register: '' }33 - { id: 1, class: gpr, preferred-register: '' }34 - { id: 2, class: gpr, preferred-register: '' }35liveins:36fixedStack:37stack:38constants:39body: |40 bb.1 (%ir-block.0):41 liveins: $edi, $esi42 43 ; ALL-LABEL: name: test_or_i844 ; ALL: liveins: $edi, $esi45 ; ALL-NEXT: {{ $}}46 ; ALL-NEXT: [[COPY:%[0-9]+]]:gr8 = COPY $dil47 ; ALL-NEXT: [[COPY1:%[0-9]+]]:gr8 = COPY $sil48 ; ALL-NEXT: [[OR8rr:%[0-9]+]]:gr8 = OR8rr [[COPY]], [[COPY1]], implicit-def dead $eflags49 ; ALL-NEXT: $al = COPY [[OR8rr]]50 ; ALL-NEXT: RET 0, implicit $al51 %0(s8) = COPY $dil52 %1(s8) = COPY $sil53 %2(s8) = G_OR %0, %154 $al = COPY %2(s8)55 RET 0, implicit $al56 57...58---59name: test_or_i1660alignment: 1661legalized: true62regBankSelected: true63registers:64 - { id: 0, class: gpr, preferred-register: '' }65 - { id: 1, class: gpr, preferred-register: '' }66 - { id: 2, class: gpr, preferred-register: '' }67liveins:68fixedStack:69stack:70constants:71body: |72 bb.1 (%ir-block.0):73 liveins: $edi, $esi74 75 ; ALL-LABEL: name: test_or_i1676 ; ALL: liveins: $edi, $esi77 ; ALL-NEXT: {{ $}}78 ; ALL-NEXT: [[COPY:%[0-9]+]]:gr16 = COPY $di79 ; ALL-NEXT: [[COPY1:%[0-9]+]]:gr16 = COPY $si80 ; ALL-NEXT: [[OR16rr:%[0-9]+]]:gr16 = OR16rr [[COPY]], [[COPY1]], implicit-def dead $eflags81 ; ALL-NEXT: $ax = COPY [[OR16rr]]82 ; ALL-NEXT: RET 0, implicit $ax83 %0(s16) = COPY $di84 %1(s16) = COPY $si85 %2(s16) = G_OR %0, %186 $ax = COPY %2(s16)87 RET 0, implicit $ax88 89...90---91name: test_or_i3292alignment: 1693legalized: true94regBankSelected: true95registers:96 - { id: 0, class: gpr, preferred-register: '' }97 - { id: 1, class: gpr, preferred-register: '' }98 - { id: 2, class: gpr, preferred-register: '' }99liveins:100fixedStack:101stack:102constants:103body: |104 bb.1 (%ir-block.0):105 liveins: $edi, $esi106 107 ; ALL-LABEL: name: test_or_i32108 ; ALL: liveins: $edi, $esi109 ; ALL-NEXT: {{ $}}110 ; ALL-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi111 ; ALL-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi112 ; ALL-NEXT: [[OR32rr:%[0-9]+]]:gr32 = OR32rr [[COPY]], [[COPY1]], implicit-def dead $eflags113 ; ALL-NEXT: $eax = COPY [[OR32rr]]114 ; ALL-NEXT: RET 0, implicit $eax115 %0(s32) = COPY $edi116 %1(s32) = COPY $esi117 %2(s32) = G_OR %0, %1118 $eax = COPY %2(s32)119 RET 0, implicit $eax120 121...122---123name: test_or_i64124alignment: 16125legalized: true126regBankSelected: true127registers:128 - { id: 0, class: gpr, preferred-register: '' }129 - { id: 1, class: gpr, preferred-register: '' }130 - { id: 2, class: gpr, preferred-register: '' }131liveins:132fixedStack:133stack:134constants:135body: |136 bb.1 (%ir-block.0):137 liveins: $rdi, $rsi138 139 ; ALL-LABEL: name: test_or_i64140 ; ALL: liveins: $rdi, $rsi141 ; ALL-NEXT: {{ $}}142 ; ALL-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi143 ; ALL-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi144 ; ALL-NEXT: [[OR64rr:%[0-9]+]]:gr64 = OR64rr [[COPY]], [[COPY1]], implicit-def dead $eflags145 ; ALL-NEXT: $rax = COPY [[OR64rr]]146 ; ALL-NEXT: RET 0, implicit $rax147 %0(s64) = COPY $rdi148 %1(s64) = COPY $rsi149 %2(s64) = G_OR %0, %1150 $rax = COPY %2(s64)151 RET 0, implicit $rax152 153...154