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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL3 4--- |5 6 define i8 @test_i8(i32 %a, i8 %f, i8 %t) {7 entry:8 %cmp = icmp sgt i32 %a, 09 br i1 %cmp, label %cond.true, label %cond.false10 11 cond.true: ; preds = %entry12 br label %cond.end13 14 cond.false: ; preds = %entry15 br label %cond.end16 17 cond.end: ; preds = %cond.false, %cond.true18 %cond = phi i8 [ %f, %cond.true ], [ %t, %cond.false ]19 ret i8 %cond20 }21 22 define i16 @test_i16(i32 %a, i16 %f, i16 %t) {23 entry:24 %cmp = icmp sgt i32 %a, 025 br i1 %cmp, label %cond.true, label %cond.false26 27 cond.true: ; preds = %entry28 br label %cond.end29 30 cond.false: ; preds = %entry31 br label %cond.end32 33 cond.end: ; preds = %cond.false, %cond.true34 %cond = phi i16 [ %f, %cond.true ], [ %t, %cond.false ]35 ret i16 %cond36 }37 38 define i32 @test_i32(i32 %a, i32 %f, i32 %t) {39 entry:40 %cmp = icmp sgt i32 %a, 041 br i1 %cmp, label %cond.true, label %cond.false42 43 cond.true: ; preds = %entry44 br label %cond.end45 46 cond.false: ; preds = %entry47 br label %cond.end48 49 cond.end: ; preds = %cond.false, %cond.true50 %cond = phi i32 [ %f, %cond.true ], [ %t, %cond.false ]51 ret i32 %cond52 }53 54 define i64 @test_i64(i32 %a, i64 %f, i64 %t) {55 entry:56 %cmp = icmp sgt i32 %a, 057 br i1 %cmp, label %cond.true, label %cond.false58 59 cond.true: ; preds = %entry60 br label %cond.end61 62 cond.false: ; preds = %entry63 br label %cond.end64 65 cond.end: ; preds = %cond.false, %cond.true66 %cond = phi i64 [ %f, %cond.true ], [ %t, %cond.false ]67 ret i64 %cond68 }69 70 define float @test_float(i32 %a, float %f, float %t) {71 entry:72 %cmp = icmp sgt i32 %a, 073 br i1 %cmp, label %cond.true, label %cond.false74 75 cond.true: ; preds = %entry76 br label %cond.end77 78 cond.false: ; preds = %entry79 br label %cond.end80 81 cond.end: ; preds = %cond.false, %cond.true82 %cond = phi float [ %f, %cond.true ], [ %t, %cond.false ]83 ret float %cond84 }85 86 define double @test_double(i32 %a, double %f, double %t) {87 entry:88 %cmp = icmp sgt i32 %a, 089 br i1 %cmp, label %cond.true, label %cond.false90 91 cond.true: ; preds = %entry92 br label %cond.end93 94 cond.false: ; preds = %entry95 br label %cond.end96 97 cond.end: ; preds = %cond.false, %cond.true98 %cond = phi double [ %f, %cond.true ], [ %t, %cond.false ]99 ret double %cond100 }101 102...103---104name: test_i8105alignment: 16106legalized: true107regBankSelected: true108tracksRegLiveness: true109registers:110 - { id: 0, class: gpr, preferred-register: '' }111 - { id: 1, class: gpr, preferred-register: '' }112 - { id: 2, class: gpr, preferred-register: '' }113 - { id: 3, class: gpr, preferred-register: '' }114 - { id: 4, class: gpr, preferred-register: '' }115 - { id: 5, class: gpr, preferred-register: '' }116 - { id: 6, class: gpr, preferred-register: '' }117 - { id: 7, class: gpr, preferred-register: '' }118body: |119 ; ALL-LABEL: name: test_i8120 ; ALL: bb.0.entry:121 ; ALL-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)122 ; ALL-NEXT: liveins: $edi, $edx, $esi123 ; ALL-NEXT: {{ $}}124 ; ALL-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi125 ; ALL-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi126 ; ALL-NEXT: [[COPY2:%[0-9]+]]:gr8 = COPY [[COPY1]].sub_8bit127 ; ALL-NEXT: [[COPY3:%[0-9]+]]:gr32 = COPY $edx128 ; ALL-NEXT: [[COPY4:%[0-9]+]]:gr8 = COPY [[COPY3]].sub_8bit129 ; ALL-NEXT: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def dead $eflags130 ; ALL-NEXT: CMP32rr [[COPY]], [[MOV32r0_]], implicit-def $eflags131 ; ALL-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 15, implicit $eflags132 ; ALL-NEXT: TEST8ri [[SETCCr]], 1, implicit-def $eflags133 ; ALL-NEXT: JCC_1 %bb.2, 5, implicit $eflags134 ; ALL-NEXT: {{ $}}135 ; ALL-NEXT: bb.1.cond.false:136 ; ALL-NEXT: successors: %bb.2(0x80000000)137 ; ALL-NEXT: {{ $}}138 ; ALL-NEXT: bb.2.cond.end:139 ; ALL-NEXT: [[PHI:%[0-9]+]]:gr8 = PHI [[COPY4]], %bb.1, [[COPY2]], %bb.0140 ; ALL-NEXT: $al = COPY [[PHI]]141 ; ALL-NEXT: RET 0, implicit $al142 bb.1.entry:143 successors: %bb.3(0x40000000), %bb.2(0x40000000)144 liveins: $edi, $edx, $esi145 146 %0:gpr(s32) = COPY $edi147 %3:gpr(s32) = COPY $esi148 %1:gpr(s8) = G_TRUNC %3(s32)149 %4:gpr(s32) = COPY $edx150 %2:gpr(s8) = G_TRUNC %4(s32)151 %5:gpr(s32) = G_CONSTANT i32 0152 %8:gpr(s8) = G_ICMP intpred(sgt), %0(s32), %5153 %6:gpr(s1) = G_TRUNC %8(s8)154 G_BRCOND %6(s1), %bb.3155 156 bb.2.cond.false:157 successors: %bb.3(0x80000000)158 159 160 bb.3.cond.end:161 %7:gpr(s8) = G_PHI %2(s8), %bb.2, %1(s8), %bb.1162 $al = COPY %7(s8)163 RET 0, implicit $al164 165...166---167name: test_i16168alignment: 16169legalized: true170regBankSelected: true171tracksRegLiveness: true172registers:173 - { id: 0, class: gpr, preferred-register: '' }174 - { id: 1, class: gpr, preferred-register: '' }175 - { id: 2, class: gpr, preferred-register: '' }176 - { id: 3, class: gpr, preferred-register: '' }177 - { id: 4, class: gpr, preferred-register: '' }178 - { id: 5, class: gpr, preferred-register: '' }179 - { id: 6, class: gpr, preferred-register: '' }180 - { id: 7, class: gpr, preferred-register: '' }181body: |182 ; ALL-LABEL: name: test_i16183 ; ALL: bb.0.entry:184 ; ALL-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)185 ; ALL-NEXT: liveins: $edi, $edx, $esi186 ; ALL-NEXT: {{ $}}187 ; ALL-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi188 ; ALL-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi189 ; ALL-NEXT: [[COPY2:%[0-9]+]]:gr16 = COPY [[COPY1]].sub_16bit190 ; ALL-NEXT: [[COPY3:%[0-9]+]]:gr32 = COPY $edx191 ; ALL-NEXT: [[COPY4:%[0-9]+]]:gr16 = COPY [[COPY3]].sub_16bit192 ; ALL-NEXT: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def dead $eflags193 ; ALL-NEXT: CMP32rr [[COPY]], [[MOV32r0_]], implicit-def $eflags194 ; ALL-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 15, implicit $eflags195 ; ALL-NEXT: TEST8ri [[SETCCr]], 1, implicit-def $eflags196 ; ALL-NEXT: JCC_1 %bb.2, 5, implicit $eflags197 ; ALL-NEXT: {{ $}}198 ; ALL-NEXT: bb.1.cond.false:199 ; ALL-NEXT: successors: %bb.2(0x80000000)200 ; ALL-NEXT: {{ $}}201 ; ALL-NEXT: bb.2.cond.end:202 ; ALL-NEXT: [[PHI:%[0-9]+]]:gr16 = PHI [[COPY4]], %bb.1, [[COPY2]], %bb.0203 ; ALL-NEXT: $ax = COPY [[PHI]]204 ; ALL-NEXT: RET 0, implicit $ax205 bb.1.entry:206 successors: %bb.3(0x40000000), %bb.2(0x40000000)207 liveins: $edi, $edx, $esi208 209 %0:gpr(s32) = COPY $edi210 %3:gpr(s32) = COPY $esi211 %1:gpr(s16) = G_TRUNC %3(s32)212 %4:gpr(s32) = COPY $edx213 %2:gpr(s16) = G_TRUNC %4(s32)214 %5:gpr(s32) = G_CONSTANT i32 0215 %8:gpr(s8) = G_ICMP intpred(sgt), %0(s32), %5216 %6:gpr(s1) = G_TRUNC %8(s8)217 G_BRCOND %6(s1), %bb.3218 219 bb.2.cond.false:220 successors: %bb.3(0x80000000)221 222 223 bb.3.cond.end:224 %7:gpr(s16) = G_PHI %2(s16), %bb.2, %1(s16), %bb.1225 $ax = COPY %7(s16)226 RET 0, implicit $ax227 228...229---230name: test_i32231alignment: 16232legalized: true233regBankSelected: true234tracksRegLiveness: true235registers:236 - { id: 0, class: gpr, preferred-register: '' }237 - { id: 1, class: gpr, preferred-register: '' }238 - { id: 2, class: gpr, preferred-register: '' }239 - { id: 3, class: gpr, preferred-register: '' }240 - { id: 4, class: gpr, preferred-register: '' }241 - { id: 5, class: gpr, preferred-register: '' }242 - { id: 6, class: gpr, preferred-register: '' }243body: |244 ; ALL-LABEL: name: test_i32245 ; ALL: bb.0.entry:246 ; ALL-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)247 ; ALL-NEXT: liveins: $edi, $edx, $esi248 ; ALL-NEXT: {{ $}}249 ; ALL-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi250 ; ALL-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi251 ; ALL-NEXT: [[COPY2:%[0-9]+]]:gr32 = COPY $edx252 ; ALL-NEXT: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def dead $eflags253 ; ALL-NEXT: CMP32rr [[COPY]], [[MOV32r0_]], implicit-def $eflags254 ; ALL-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 15, implicit $eflags255 ; ALL-NEXT: TEST8ri [[SETCCr]], 1, implicit-def $eflags256 ; ALL-NEXT: JCC_1 %bb.1, 5, implicit $eflags257 ; ALL-NEXT: JMP_1 %bb.2258 ; ALL-NEXT: {{ $}}259 ; ALL-NEXT: bb.1.cond.true:260 ; ALL-NEXT: successors: %bb.3(0x80000000)261 ; ALL-NEXT: {{ $}}262 ; ALL-NEXT: JMP_1 %bb.3263 ; ALL-NEXT: {{ $}}264 ; ALL-NEXT: bb.2.cond.false:265 ; ALL-NEXT: successors: %bb.3(0x80000000)266 ; ALL-NEXT: {{ $}}267 ; ALL-NEXT: bb.3.cond.end:268 ; ALL-NEXT: [[PHI:%[0-9]+]]:gr32 = PHI [[COPY1]], %bb.1, [[COPY2]], %bb.2269 ; ALL-NEXT: $eax = COPY [[PHI]]270 ; ALL-NEXT: RET 0, implicit $eax271 bb.1.entry:272 successors: %bb.2(0x40000000), %bb.3(0x40000000)273 liveins: $edi, $edx, $esi274 275 %0(s32) = COPY $edi276 %1(s32) = COPY $esi277 %2(s32) = COPY $edx278 %3(s32) = G_CONSTANT i32 0279 %6(s8) = G_ICMP intpred(sgt), %0(s32), %3280 %4:gpr(s1) = G_TRUNC %6(s8)281 G_BRCOND %4(s1), %bb.2282 G_BR %bb.3283 284 bb.2.cond.true:285 successors: %bb.4(0x80000000)286 287 G_BR %bb.4288 289 bb.3.cond.false:290 successors: %bb.4(0x80000000)291 292 293 bb.4.cond.end:294 %5(s32) = G_PHI %1(s32), %bb.2, %2(s32), %bb.3295 $eax = COPY %5(s32)296 RET 0, implicit $eax297 298...299---300name: test_i64301alignment: 16302legalized: true303regBankSelected: true304tracksRegLiveness: true305registers:306 - { id: 0, class: gpr, preferred-register: '' }307 - { id: 1, class: gpr, preferred-register: '' }308 - { id: 2, class: gpr, preferred-register: '' }309 - { id: 3, class: gpr, preferred-register: '' }310 - { id: 4, class: gpr, preferred-register: '' }311 - { id: 5, class: gpr, preferred-register: '' }312 - { id: 6, class: gpr, preferred-register: '' }313body: |314 ; ALL-LABEL: name: test_i64315 ; ALL: bb.0.entry:316 ; ALL-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)317 ; ALL-NEXT: liveins: $edi, $rdx, $rsi318 ; ALL-NEXT: {{ $}}319 ; ALL-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi320 ; ALL-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi321 ; ALL-NEXT: [[COPY2:%[0-9]+]]:gr64 = COPY $rdx322 ; ALL-NEXT: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def dead $eflags323 ; ALL-NEXT: CMP32rr [[COPY]], [[MOV32r0_]], implicit-def $eflags324 ; ALL-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 15, implicit $eflags325 ; ALL-NEXT: TEST8ri [[SETCCr]], 1, implicit-def $eflags326 ; ALL-NEXT: JCC_1 %bb.1, 5, implicit $eflags327 ; ALL-NEXT: JMP_1 %bb.2328 ; ALL-NEXT: {{ $}}329 ; ALL-NEXT: bb.1.cond.true:330 ; ALL-NEXT: successors: %bb.3(0x80000000)331 ; ALL-NEXT: {{ $}}332 ; ALL-NEXT: JMP_1 %bb.3333 ; ALL-NEXT: {{ $}}334 ; ALL-NEXT: bb.2.cond.false:335 ; ALL-NEXT: successors: %bb.3(0x80000000)336 ; ALL-NEXT: {{ $}}337 ; ALL-NEXT: bb.3.cond.end:338 ; ALL-NEXT: [[PHI:%[0-9]+]]:gr64 = PHI [[COPY1]], %bb.1, [[COPY2]], %bb.2339 ; ALL-NEXT: $rax = COPY [[PHI]]340 ; ALL-NEXT: RET 0, implicit $rax341 bb.1.entry:342 successors: %bb.2(0x40000000), %bb.3(0x40000000)343 liveins: $edi, $rdx, $rsi344 345 %0(s32) = COPY $edi346 %1(s64) = COPY $rsi347 %2(s64) = COPY $rdx348 %3(s32) = G_CONSTANT i32 0349 %6(s8) = G_ICMP intpred(sgt), %0(s32), %3350 %4:gpr(s1) = G_TRUNC %6(s8)351 G_BRCOND %4(s1), %bb.2352 G_BR %bb.3353 354 bb.2.cond.true:355 successors: %bb.4(0x80000000)356 357 G_BR %bb.4358 359 bb.3.cond.false:360 successors: %bb.4(0x80000000)361 362 363 bb.4.cond.end:364 %5(s64) = G_PHI %1(s64), %bb.2, %2(s64), %bb.3365 $rax = COPY %5(s64)366 RET 0, implicit $rax367 368...369---370name: test_float371alignment: 16372legalized: true373regBankSelected: true374tracksRegLiveness: true375registers:376 - { id: 0, class: gpr, preferred-register: '' }377 - { id: 1, class: vecr, preferred-register: '' }378 - { id: 2, class: vecr, preferred-register: '' }379 - { id: 3, class: vecr, preferred-register: '' }380 - { id: 4, class: vecr, preferred-register: '' }381 - { id: 5, class: gpr, preferred-register: '' }382 - { id: 6, class: gpr, preferred-register: '' }383 - { id: 7, class: vecr, preferred-register: '' }384 - { id: 8, class: vecr, preferred-register: '' }385liveins:386fixedStack:387stack:388constants:389body: |390 ; ALL-LABEL: name: test_float391 ; ALL: bb.0.entry:392 ; ALL-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)393 ; ALL-NEXT: liveins: $edi, $xmm0, $xmm1394 ; ALL-NEXT: {{ $}}395 ; ALL-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi396 ; ALL-NEXT: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0397 ; ALL-NEXT: [[COPY2:%[0-9]+]]:fr32 = COPY [[COPY1]]398 ; ALL-NEXT: [[COPY3:%[0-9]+]]:vr128 = COPY $xmm1399 ; ALL-NEXT: [[COPY4:%[0-9]+]]:fr32 = COPY [[COPY3]]400 ; ALL-NEXT: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def dead $eflags401 ; ALL-NEXT: CMP32rr [[COPY]], [[MOV32r0_]], implicit-def $eflags402 ; ALL-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 15, implicit $eflags403 ; ALL-NEXT: TEST8ri [[SETCCr]], 1, implicit-def $eflags404 ; ALL-NEXT: JCC_1 %bb.2, 5, implicit $eflags405 ; ALL-NEXT: {{ $}}406 ; ALL-NEXT: bb.1.cond.false:407 ; ALL-NEXT: successors: %bb.2(0x80000000)408 ; ALL-NEXT: {{ $}}409 ; ALL-NEXT: bb.2.cond.end:410 ; ALL-NEXT: [[PHI:%[0-9]+]]:fr32 = PHI [[COPY4]], %bb.1, [[COPY2]], %bb.0411 ; ALL-NEXT: [[COPY5:%[0-9]+]]:vr128 = COPY [[PHI]]412 ; ALL-NEXT: $xmm0 = COPY [[COPY5]]413 ; ALL-NEXT: RET 0, implicit $xmm0414 bb.1.entry:415 successors: %bb.3(0x40000000), %bb.2(0x40000000)416 liveins: $edi, $xmm0, $xmm1417 418 %0:gpr(s32) = COPY $edi419 %3:vecr(s128) = COPY $xmm0420 %1:vecr(s32) = G_TRUNC %3(s128)421 %4:vecr(s128) = COPY $xmm1422 %2:vecr(s32) = G_TRUNC %4(s128)423 %5:gpr(s32) = G_CONSTANT i32 0424 %9:gpr(s8) = G_ICMP intpred(sgt), %0(s32), %5425 %6:gpr(s1) = G_TRUNC %9(s8)426 G_BRCOND %6(s1), %bb.3427 428 bb.2.cond.false:429 successors: %bb.3(0x80000000)430 431 bb.3.cond.end:432 %7:vecr(s32) = G_PHI %2(s32), %bb.2, %1(s32), %bb.1433 %8:vecr(s128) = G_ANYEXT %7(s32)434 $xmm0 = COPY %8(s128)435 RET 0, implicit $xmm0436 437...438---439name: test_double440alignment: 16441legalized: true442regBankSelected: true443tracksRegLiveness: true444registers:445 - { id: 0, class: gpr, preferred-register: '' }446 - { id: 1, class: vecr, preferred-register: '' }447 - { id: 2, class: vecr, preferred-register: '' }448 - { id: 3, class: vecr, preferred-register: '' }449 - { id: 4, class: vecr, preferred-register: '' }450 - { id: 5, class: gpr, preferred-register: '' }451 - { id: 6, class: gpr, preferred-register: '' }452 - { id: 7, class: vecr, preferred-register: '' }453 - { id: 8, class: vecr, preferred-register: '' }454body: |455 ; ALL-LABEL: name: test_double456 ; ALL: bb.0.entry:457 ; ALL-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)458 ; ALL-NEXT: liveins: $edi, $xmm0, $xmm1459 ; ALL-NEXT: {{ $}}460 ; ALL-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi461 ; ALL-NEXT: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0462 ; ALL-NEXT: [[COPY2:%[0-9]+]]:fr64 = COPY [[COPY1]]463 ; ALL-NEXT: [[COPY3:%[0-9]+]]:vr128 = COPY $xmm1464 ; ALL-NEXT: [[COPY4:%[0-9]+]]:fr64 = COPY [[COPY3]]465 ; ALL-NEXT: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def dead $eflags466 ; ALL-NEXT: CMP32rr [[COPY]], [[MOV32r0_]], implicit-def $eflags467 ; ALL-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 15, implicit $eflags468 ; ALL-NEXT: TEST8ri [[SETCCr]], 1, implicit-def $eflags469 ; ALL-NEXT: JCC_1 %bb.2, 5, implicit $eflags470 ; ALL-NEXT: {{ $}}471 ; ALL-NEXT: bb.1.cond.false:472 ; ALL-NEXT: successors: %bb.2(0x80000000)473 ; ALL-NEXT: {{ $}}474 ; ALL-NEXT: bb.2.cond.end:475 ; ALL-NEXT: [[PHI:%[0-9]+]]:fr64 = PHI [[COPY4]], %bb.1, [[COPY2]], %bb.0476 ; ALL-NEXT: [[COPY5:%[0-9]+]]:vr128 = COPY [[PHI]]477 ; ALL-NEXT: $xmm0 = COPY [[COPY5]]478 ; ALL-NEXT: RET 0, implicit $xmm0479 bb.1.entry:480 successors: %bb.3(0x40000000), %bb.2(0x40000000)481 liveins: $edi, $xmm0, $xmm1482 483 %0:gpr(s32) = COPY $edi484 %3:vecr(s128) = COPY $xmm0485 %1:vecr(s64) = G_TRUNC %3(s128)486 %4:vecr(s128) = COPY $xmm1487 %2:vecr(s64) = G_TRUNC %4(s128)488 %5:gpr(s32) = G_CONSTANT i32 0489 %9:gpr(s8) = G_ICMP intpred(sgt), %0(s32), %5490 %6:gpr(s1) = G_TRUNC %9(s8)491 G_BRCOND %6(s1), %bb.3492 493 bb.2.cond.false:494 successors: %bb.3(0x80000000)495 496 bb.3.cond.end:497 %7:vecr(s64) = G_PHI %2(s64), %bb.2, %1(s64), %bb.1498 %8:vecr(s128) = G_ANYEXT %7(s64)499 $xmm0 = COPY %8(s128)500 RET 0, implicit $xmm0501 502...503