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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL3--- |4 5 define i64 @test_shl_i64(i64 %arg1, i64 %arg2) {6 %res = shl i64 %arg1, %arg27 ret i64 %res8 }9 10 define i64 @test_shl_i64_imm(i64 %arg1) {11 %res = shl i64 %arg1, 512 ret i64 %res13 }14 15 define i64 @test_shl_i64_imm1(i64 %arg1) {16 %res = shl i64 %arg1, 117 ret i64 %res18 }19 20 define i32 @test_shl_i32(i32 %arg1, i32 %arg2) {21 %res = shl i32 %arg1, %arg222 ret i32 %res23 }24 25 define i32 @test_shl_i32_imm(i32 %arg1) {26 %res = shl i32 %arg1, 527 ret i32 %res28 }29 30 define i32 @test_shl_i32_imm1(i32 %arg1) {31 %res = shl i32 %arg1, 132 ret i32 %res33 }34 35 define i16 @test_shl_i16(i32 %arg1, i32 %arg2) {36 %a = trunc i32 %arg1 to i1637 %a2 = trunc i32 %arg2 to i1638 %res = shl i16 %a, %a239 ret i16 %res40 }41 42 define i16 @test_shl_i16_imm(i32 %arg1) {43 %a = trunc i32 %arg1 to i1644 %res = shl i16 %a, 545 ret i16 %res46 }47 48 define i16 @test_shl_i16_imm1(i32 %arg1) {49 %a = trunc i32 %arg1 to i1650 %res = shl i16 %a, 151 ret i16 %res52 }53 54 define i8 @test_shl_i8(i32 %arg1, i32 %arg2) {55 %a = trunc i32 %arg1 to i856 %a2 = trunc i32 %arg2 to i857 %res = shl i8 %a, %a258 ret i8 %res59 }60 61 define i8 @test_shl_i8_imm(i32 %arg1) {62 %a = trunc i32 %arg1 to i863 %res = shl i8 %a, 564 ret i8 %res65 }66 67 define i8 @test_shl_i8_imm1(i32 %arg1) {68 %a = trunc i32 %arg1 to i869 %res = shl i8 %a, 170 ret i8 %res71 }72 73...74---75name: test_shl_i6476alignment: 1677legalized: true78regBankSelected: true79tracksRegLiveness: true80registers:81 - { id: 0, class: gpr, preferred-register: '' }82 - { id: 1, class: gpr, preferred-register: '' }83 - { id: 2, class: gpr, preferred-register: '' }84 - { id: 3, class: gpr, preferred-register: '' }85liveins:86fixedStack:87stack:88constants:89body: |90 bb.1 (%ir-block.0):91 liveins: $rdi, $rsi92 93 ; ALL-LABEL: name: test_shl_i6494 ; ALL: liveins: $rdi, $rsi95 ; ALL-NEXT: {{ $}}96 ; ALL-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi97 ; ALL-NEXT: [[COPY1:%[0-9]+]]:gr64_with_sub_8bit = COPY $rsi98 ; ALL-NEXT: [[COPY2:%[0-9]+]]:gr8 = COPY [[COPY1]].sub_8bit99 ; ALL-NEXT: $cl = COPY [[COPY2]]100 ; ALL-NEXT: [[SHL64rCL:%[0-9]+]]:gr64 = SHL64rCL [[COPY]], implicit-def dead $eflags, implicit $cl101 ; ALL-NEXT: $rax = COPY [[SHL64rCL]]102 ; ALL-NEXT: RET 0, implicit $rax103 %0(s64) = COPY $rdi104 %1(s64) = COPY $rsi105 %2(s8) = G_TRUNC %1106 %3(s64) = G_SHL %0, %2107 $rax = COPY %3(s64)108 RET 0, implicit $rax109 110...111---112name: test_shl_i64_imm113alignment: 16114legalized: true115regBankSelected: true116tracksRegLiveness: true117registers:118 - { id: 0, class: gpr, preferred-register: '' }119 - { id: 1, class: gpr, preferred-register: '' }120 - { id: 2, class: gpr, preferred-register: '' }121liveins:122fixedStack:123stack:124constants:125body: |126 bb.1 (%ir-block.0):127 liveins: $rdi128 129 ; ALL-LABEL: name: test_shl_i64_imm130 ; ALL: liveins: $rdi131 ; ALL-NEXT: {{ $}}132 ; ALL-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi133 ; ALL-NEXT: [[SHL64ri:%[0-9]+]]:gr64 = SHL64ri [[COPY]], 5, implicit-def dead $eflags134 ; ALL-NEXT: $rax = COPY [[SHL64ri]]135 ; ALL-NEXT: RET 0, implicit $rax136 %0(s64) = COPY $rdi137 %1(s8) = G_CONSTANT i8 5138 %2(s64) = G_SHL %0, %1139 $rax = COPY %2(s64)140 RET 0, implicit $rax141 142...143---144name: test_shl_i64_imm1145alignment: 16146legalized: true147regBankSelected: true148tracksRegLiveness: true149registers:150 - { id: 0, class: gpr, preferred-register: '' }151 - { id: 1, class: gpr, preferred-register: '' }152 - { id: 2, class: gpr, preferred-register: '' }153liveins:154fixedStack:155stack:156constants:157body: |158 bb.1 (%ir-block.0):159 liveins: $rdi160 161 ; ALL-LABEL: name: test_shl_i64_imm1162 ; ALL: liveins: $rdi163 ; ALL-NEXT: {{ $}}164 ; ALL-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi165 ; ALL-NEXT: [[ADD64rr:%[0-9]+]]:gr64 = ADD64rr [[COPY]], [[COPY]], implicit-def dead $eflags166 ; ALL-NEXT: $rax = COPY [[ADD64rr]]167 ; ALL-NEXT: RET 0, implicit $rax168 %0(s64) = COPY $rdi169 %1(s8) = G_CONSTANT i8 1170 %2(s64) = G_SHL %0, %1171 $rax = COPY %2(s64)172 RET 0, implicit $rax173 174...175---176name: test_shl_i32177alignment: 16178legalized: true179regBankSelected: true180tracksRegLiveness: true181registers:182 - { id: 0, class: gpr, preferred-register: '' }183 - { id: 1, class: gpr, preferred-register: '' }184 - { id: 2, class: gpr, preferred-register: '' }185 - { id: 3, class: gpr, preferred-register: '' }186liveins:187fixedStack:188stack:189constants:190body: |191 bb.1 (%ir-block.0):192 liveins: $edi, $esi193 194 ; ALL-LABEL: name: test_shl_i32195 ; ALL: liveins: $edi, $esi196 ; ALL-NEXT: {{ $}}197 ; ALL-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi198 ; ALL-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi199 ; ALL-NEXT: [[COPY2:%[0-9]+]]:gr8 = COPY [[COPY1]].sub_8bit200 ; ALL-NEXT: $cl = COPY [[COPY2]]201 ; ALL-NEXT: [[SHL32rCL:%[0-9]+]]:gr32 = SHL32rCL [[COPY]], implicit-def dead $eflags, implicit $cl202 ; ALL-NEXT: $eax = COPY [[SHL32rCL]]203 ; ALL-NEXT: RET 0, implicit $eax204 %0(s32) = COPY $edi205 %1(s32) = COPY $esi206 %2(s8) = G_TRUNC %1207 %3(s32) = G_SHL %0, %2208 $eax = COPY %3(s32)209 RET 0, implicit $eax210 211...212---213name: test_shl_i32_imm214alignment: 16215legalized: true216regBankSelected: true217tracksRegLiveness: true218registers:219 - { id: 0, class: gpr, preferred-register: '' }220 - { id: 1, class: gpr, preferred-register: '' }221 - { id: 2, class: gpr, preferred-register: '' }222liveins:223fixedStack:224stack:225constants:226body: |227 bb.1 (%ir-block.0):228 liveins: $edi229 230 ; ALL-LABEL: name: test_shl_i32_imm231 ; ALL: liveins: $edi232 ; ALL-NEXT: {{ $}}233 ; ALL-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi234 ; ALL-NEXT: [[SHL32ri:%[0-9]+]]:gr32 = SHL32ri [[COPY]], 5, implicit-def dead $eflags235 ; ALL-NEXT: $eax = COPY [[SHL32ri]]236 ; ALL-NEXT: RET 0, implicit $eax237 %0(s32) = COPY $edi238 %1(s8) = G_CONSTANT i8 5239 %2(s32) = G_SHL %0, %1240 $eax = COPY %2(s32)241 RET 0, implicit $eax242 243...244---245name: test_shl_i32_imm1246alignment: 16247legalized: true248regBankSelected: true249tracksRegLiveness: true250registers:251 - { id: 0, class: gpr, preferred-register: '' }252 - { id: 1, class: gpr, preferred-register: '' }253 - { id: 2, class: gpr, preferred-register: '' }254liveins:255fixedStack:256stack:257constants:258body: |259 bb.1 (%ir-block.0):260 liveins: $edi261 262 ; ALL-LABEL: name: test_shl_i32_imm1263 ; ALL: liveins: $edi264 ; ALL-NEXT: {{ $}}265 ; ALL-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi266 ; ALL-NEXT: [[ADD32rr:%[0-9]+]]:gr32 = ADD32rr [[COPY]], [[COPY]], implicit-def dead $eflags267 ; ALL-NEXT: $eax = COPY [[ADD32rr]]268 ; ALL-NEXT: RET 0, implicit $eax269 %0(s32) = COPY $edi270 %1(s8) = G_CONSTANT i8 1271 %2(s32) = G_SHL %0, %1272 $eax = COPY %2(s32)273 RET 0, implicit $eax274 275...276---277name: test_shl_i16278alignment: 16279legalized: true280regBankSelected: true281tracksRegLiveness: true282registers:283 - { id: 0, class: gpr, preferred-register: '' }284 - { id: 1, class: gpr, preferred-register: '' }285 - { id: 2, class: gpr, preferred-register: '' }286 - { id: 3, class: gpr, preferred-register: '' }287 - { id: 4, class: gpr, preferred-register: '' }288liveins:289fixedStack:290stack:291constants:292body: |293 bb.1 (%ir-block.0):294 liveins: $edi, $esi295 296 ; ALL-LABEL: name: test_shl_i16297 ; ALL: liveins: $edi, $esi298 ; ALL-NEXT: {{ $}}299 ; ALL-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi300 ; ALL-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi301 ; ALL-NEXT: [[COPY2:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit302 ; ALL-NEXT: [[COPY3:%[0-9]+]]:gr8 = COPY [[COPY1]].sub_8bit303 ; ALL-NEXT: $cl = COPY [[COPY3]]304 ; ALL-NEXT: [[SHL16rCL:%[0-9]+]]:gr16 = SHL16rCL [[COPY2]], implicit-def dead $eflags, implicit $cl305 ; ALL-NEXT: $ax = COPY [[SHL16rCL]]306 ; ALL-NEXT: RET 0, implicit $ax307 %0(s32) = COPY $edi308 %1(s32) = COPY $esi309 %2(s16) = G_TRUNC %0(s32)310 %3(s8) = G_TRUNC %1(s32)311 %4(s16) = G_SHL %2, %3312 $ax = COPY %4(s16)313 RET 0, implicit $ax314 315...316---317name: test_shl_i16_imm318alignment: 16319legalized: true320regBankSelected: true321tracksRegLiveness: true322registers:323 - { id: 0, class: gpr, preferred-register: '' }324 - { id: 1, class: gpr, preferred-register: '' }325 - { id: 2, class: gpr, preferred-register: '' }326 - { id: 3, class: gpr, preferred-register: '' }327liveins:328fixedStack:329stack:330constants:331body: |332 bb.1 (%ir-block.0):333 liveins: $edi334 335 ; ALL-LABEL: name: test_shl_i16_imm336 ; ALL: liveins: $edi337 ; ALL-NEXT: {{ $}}338 ; ALL-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi339 ; ALL-NEXT: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit340 ; ALL-NEXT: [[SHL16ri:%[0-9]+]]:gr16 = SHL16ri [[COPY1]], 5, implicit-def dead $eflags341 ; ALL-NEXT: $ax = COPY [[SHL16ri]]342 ; ALL-NEXT: RET 0, implicit $ax343 %0(s32) = COPY $edi344 %2(s8) = G_CONSTANT i8 5345 %1(s16) = G_TRUNC %0(s32)346 %3(s16) = G_SHL %1, %2347 $ax = COPY %3(s16)348 RET 0, implicit $ax349 350...351---352name: test_shl_i16_imm1353alignment: 16354legalized: true355regBankSelected: true356tracksRegLiveness: true357registers:358 - { id: 0, class: gpr, preferred-register: '' }359 - { id: 1, class: gpr, preferred-register: '' }360 - { id: 2, class: gpr, preferred-register: '' }361 - { id: 3, class: gpr, preferred-register: '' }362liveins:363fixedStack:364stack:365constants:366body: |367 bb.1 (%ir-block.0):368 liveins: $edi369 370 ; ALL-LABEL: name: test_shl_i16_imm1371 ; ALL: liveins: $edi372 ; ALL-NEXT: {{ $}}373 ; ALL-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi374 ; ALL-NEXT: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit375 ; ALL-NEXT: [[ADD16rr:%[0-9]+]]:gr16 = ADD16rr [[COPY1]], [[COPY1]], implicit-def dead $eflags376 ; ALL-NEXT: $ax = COPY [[ADD16rr]]377 ; ALL-NEXT: RET 0, implicit $ax378 %0(s32) = COPY $edi379 %2(s8) = G_CONSTANT i8 1380 %1(s16) = G_TRUNC %0(s32)381 %3(s16) = G_SHL %1, %2382 $ax = COPY %3(s16)383 RET 0, implicit $ax384 385...386---387name: test_shl_i8388alignment: 16389legalized: true390regBankSelected: true391tracksRegLiveness: true392registers:393 - { id: 0, class: gpr, preferred-register: '' }394 - { id: 1, class: gpr, preferred-register: '' }395 - { id: 2, class: gpr, preferred-register: '' }396 - { id: 3, class: gpr, preferred-register: '' }397 - { id: 4, class: gpr, preferred-register: '' }398liveins:399fixedStack:400stack:401constants:402body: |403 bb.1 (%ir-block.0):404 liveins: $edi, $esi405 406 ; ALL-LABEL: name: test_shl_i8407 ; ALL: liveins: $edi, $esi408 ; ALL-NEXT: {{ $}}409 ; ALL-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi410 ; ALL-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi411 ; ALL-NEXT: [[COPY2:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit412 ; ALL-NEXT: [[COPY3:%[0-9]+]]:gr8 = COPY [[COPY1]].sub_8bit413 ; ALL-NEXT: $cl = COPY [[COPY3]]414 ; ALL-NEXT: [[SHL8rCL:%[0-9]+]]:gr8 = SHL8rCL [[COPY2]], implicit-def dead $eflags, implicit $cl415 ; ALL-NEXT: $al = COPY [[SHL8rCL]]416 ; ALL-NEXT: RET 0, implicit $al417 %0(s32) = COPY $edi418 %1(s32) = COPY $esi419 %2(s8) = G_TRUNC %0(s32)420 %3(s8) = G_TRUNC %1(s32)421 %4(s8) = G_SHL %2, %3422 $al = COPY %4(s8)423 RET 0, implicit $al424 425...426---427name: test_shl_i8_imm428alignment: 16429legalized: true430regBankSelected: true431tracksRegLiveness: true432registers:433 - { id: 0, class: gpr, preferred-register: '' }434 - { id: 1, class: gpr, preferred-register: '' }435 - { id: 2, class: gpr, preferred-register: '' }436 - { id: 3, class: gpr, preferred-register: '' }437liveins:438fixedStack:439stack:440constants:441body: |442 bb.1 (%ir-block.0):443 liveins: $edi444 445 ; ALL-LABEL: name: test_shl_i8_imm446 ; ALL: liveins: $edi447 ; ALL-NEXT: {{ $}}448 ; ALL-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi449 ; ALL-NEXT: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit450 ; ALL-NEXT: [[SHL8ri:%[0-9]+]]:gr8 = SHL8ri [[COPY1]], 5, implicit-def dead $eflags451 ; ALL-NEXT: $al = COPY [[SHL8ri]]452 ; ALL-NEXT: RET 0, implicit $al453 %0(s32) = COPY $edi454 %2(s8) = G_CONSTANT i8 5455 %1(s8) = G_TRUNC %0(s32)456 %3(s8) = G_SHL %1, %2457 $al = COPY %3(s8)458 RET 0, implicit $al459 460...461---462name: test_shl_i8_imm1463alignment: 16464legalized: true465regBankSelected: true466tracksRegLiveness: true467registers:468 - { id: 0, class: gpr, preferred-register: '' }469 - { id: 1, class: gpr, preferred-register: '' }470 - { id: 2, class: gpr, preferred-register: '' }471 - { id: 3, class: gpr, preferred-register: '' }472liveins:473fixedStack:474stack:475constants:476body: |477 bb.1 (%ir-block.0):478 liveins: $edi479 480 ; ALL-LABEL: name: test_shl_i8_imm1481 ; ALL: liveins: $edi482 ; ALL-NEXT: {{ $}}483 ; ALL-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi484 ; ALL-NEXT: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit485 ; ALL-NEXT: [[ADD8rr:%[0-9]+]]:gr8 = ADD8rr [[COPY1]], [[COPY1]], implicit-def dead $eflags486 ; ALL-NEXT: $al = COPY [[ADD8rr]]487 ; ALL-NEXT: RET 0, implicit $al488 %0(s32) = COPY $edi489 %2(s8) = G_CONSTANT i8 1490 %1(s8) = G_TRUNC %0(s32)491 %3(s8) = G_SHL %1, %2492 $al = COPY %3(s8)493 RET 0, implicit $al494 495...496