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1# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+sse2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=ALL,SSE22# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=ALL,AVX13# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f,+avx512vl -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=ALL,AVX512VL4# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f,+avx512vl,+avx512bw -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=ALL,AVX512BWVL5 6--- |7 define <16 x i8> @test_sub_v16i8(<16 x i8> %arg1, <16 x i8> %arg2) {8 %ret = sub <16 x i8> %arg1, %arg29 ret <16 x i8> %ret10 }11 12 define <8 x i16> @test_sub_v8i16(<8 x i16> %arg1, <8 x i16> %arg2) {13 %ret = sub <8 x i16> %arg1, %arg214 ret <8 x i16> %ret15 }16 17 define <4 x i32> @test_sub_v4i32(<4 x i32> %arg1, <4 x i32> %arg2) {18 %ret = sub <4 x i32> %arg1, %arg219 ret <4 x i32> %ret20 }21 22 define <2 x i64> @test_sub_v2i64(<2 x i64> %arg1, <2 x i64> %arg2) {23 %ret = sub <2 x i64> %arg1, %arg224 ret <2 x i64> %ret25 }26 27...28---29name: test_sub_v16i830# ALL-LABEL: name: test_sub_v16i831alignment: 1632legalized: true33regBankSelected: true34registers:35 - { id: 0, class: vecr }36 - { id: 1, class: vecr }37 - { id: 2, class: vecr }38# SSE2: %2:vr128 = PSUBBrr %0, %139#40# AVX1: %2:vr128 = VPSUBBrr %0, %141#42# AVX512VL: %2:vr128 = VPSUBBrr %0, %143#44# AVX512BWVL: %2:vr128x = VPSUBBZ128rr %0, %145body: |46 bb.1 (%ir-block.0):47 liveins: $xmm0, $xmm148 49 %0(<16 x s8>) = COPY $xmm050 %1(<16 x s8>) = COPY $xmm151 %2(<16 x s8>) = G_SUB %0, %152 $xmm0 = COPY %2(<16 x s8>)53 RET 0, implicit $xmm054 55...56---57name: test_sub_v8i1658# ALL-LABEL: name: test_sub_v8i1659alignment: 1660legalized: true61regBankSelected: true62registers:63 - { id: 0, class: vecr }64 - { id: 1, class: vecr }65 - { id: 2, class: vecr }66# SSE2: %2:vr128 = PSUBWrr %0, %167#68# AVX1: %2:vr128 = VPSUBWrr %0, %169#70# AVX512VL: %2:vr128 = VPSUBWrr %0, %171#72# AVX512BWVL: %2:vr128x = VPSUBWZ128rr %0, %173body: |74 bb.1 (%ir-block.0):75 liveins: $xmm0, $xmm176 77 %0(<8 x s16>) = COPY $xmm078 %1(<8 x s16>) = COPY $xmm179 %2(<8 x s16>) = G_SUB %0, %180 $xmm0 = COPY %2(<8 x s16>)81 RET 0, implicit $xmm082 83...84---85name: test_sub_v4i3286# ALL-LABEL: name: test_sub_v4i3287alignment: 1688legalized: true89regBankSelected: true90registers:91 - { id: 0, class: vecr }92 - { id: 1, class: vecr }93 - { id: 2, class: vecr }94# SSE2: %2:vr128 = PSUBDrr %0, %195#96# AVX1: %2:vr128 = VPSUBDrr %0, %197#98# AVX512VL: %2:vr128x = VPSUBDZ128rr %0, %199#100# AVX512BWVL: %2:vr128x = VPSUBDZ128rr %0, %1101body: |102 bb.1 (%ir-block.0):103 liveins: $xmm0, $xmm1104 105 %0(<4 x s32>) = COPY $xmm0106 %1(<4 x s32>) = COPY $xmm1107 %2(<4 x s32>) = G_SUB %0, %1108 $xmm0 = COPY %2(<4 x s32>)109 RET 0, implicit $xmm0110 111...112---113name: test_sub_v2i64114# ALL-LABEL: name: test_sub_v2i64115alignment: 16116legalized: true117regBankSelected: true118registers:119 - { id: 0, class: vecr }120 - { id: 1, class: vecr }121 - { id: 2, class: vecr }122# SSE2: %2:vr128 = PSUBQrr %0, %1123#124# AVX1: %2:vr128 = VPSUBQrr %0, %1125#126# AVX512VL: %2:vr128x = VPSUBQZ128rr %0, %1127#128# AVX512BWVL: %2:vr128x = VPSUBQZ128rr %0, %1129body: |130 bb.1 (%ir-block.0):131 liveins: $xmm0, $xmm1132 133 %0(<2 x s64>) = COPY $xmm0134 %1(<2 x s64>) = COPY $xmm1135 %2(<2 x s64>) = G_SUB %0, %1136 $xmm0 = COPY %2(<2 x s64>)137 RET 0, implicit $xmm0138 139...140