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1# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=AVX22# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f,+avx512vl -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=AVX512VL3# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f,+avx512vl,+avx512bw -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=AVX512BWVL4 5--- |6 define <32 x i8> @test_sub_v32i8(<32 x i8> %arg1, <32 x i8> %arg2) {7 %ret = sub <32 x i8> %arg1, %arg28 ret <32 x i8> %ret9 }10 11 define <16 x i16> @test_sub_v16i16(<16 x i16> %arg1, <16 x i16> %arg2) {12 %ret = sub <16 x i16> %arg1, %arg213 ret <16 x i16> %ret14 }15 16 define <8 x i32> @test_sub_v8i32(<8 x i32> %arg1, <8 x i32> %arg2) {17 %ret = sub <8 x i32> %arg1, %arg218 ret <8 x i32> %ret19 }20 21 define <4 x i64> @test_sub_v4i64(<4 x i64> %arg1, <4 x i64> %arg2) {22 %ret = sub <4 x i64> %arg1, %arg223 ret <4 x i64> %ret24 }25...26---27name: test_sub_v32i828# ALL-LABEL: name: test_sub_v32i829alignment: 1630legalized: true31regBankSelected: true32registers:33 - { id: 0, class: vecr }34 - { id: 1, class: vecr }35 - { id: 2, class: vecr }36# AVX2: %2:vr256 = VPSUBBYrr %0, %137#38# AVX512VL: %2:vr256 = VPSUBBYrr %0, %139#40# AVX512BWVL: %2:vr256x = VPSUBBZ256rr %0, %141body: |42 bb.1 (%ir-block.0):43 liveins: $ymm0, $ymm144 45 %0(<32 x s8>) = COPY $ymm046 %1(<32 x s8>) = COPY $ymm147 %2(<32 x s8>) = G_SUB %0, %148 $ymm0 = COPY %2(<32 x s8>)49 RET 0, implicit $ymm050 51...52---53name: test_sub_v16i1654# ALL-LABEL: name: test_sub_v16i1655alignment: 1656legalized: true57regBankSelected: true58registers:59 - { id: 0, class: vecr }60 - { id: 1, class: vecr }61 - { id: 2, class: vecr }62# AVX2: %2:vr256 = VPSUBWYrr %0, %163#64# AVX512VL: %2:vr256 = VPSUBWYrr %0, %165#66# AVX512BWVL: %2:vr256x = VPSUBWZ256rr %0, %167body: |68 bb.1 (%ir-block.0):69 liveins: $ymm0, $ymm170 71 %0(<16 x s16>) = COPY $ymm072 %1(<16 x s16>) = COPY $ymm173 %2(<16 x s16>) = G_SUB %0, %174 $ymm0 = COPY %2(<16 x s16>)75 RET 0, implicit $ymm076 77...78---79name: test_sub_v8i3280# ALL-LABEL: name: test_sub_v8i3281alignment: 1682legalized: true83regBankSelected: true84registers:85 - { id: 0, class: vecr }86 - { id: 1, class: vecr }87 - { id: 2, class: vecr }88# AVX2: %2:vr256 = VPSUBDYrr %0, %189#90# AVX512VL: %2:vr256x = VPSUBDZ256rr %0, %191#92# AVX512BWVL: %2:vr256x = VPSUBDZ256rr %0, %193body: |94 bb.1 (%ir-block.0):95 liveins: $ymm0, $ymm196 97 %0(<8 x s32>) = COPY $ymm098 %1(<8 x s32>) = COPY $ymm199 %2(<8 x s32>) = G_SUB %0, %1100 $ymm0 = COPY %2(<8 x s32>)101 RET 0, implicit $ymm0102 103...104---105name: test_sub_v4i64106# ALL-LABEL: name: test_sub_v4i64107alignment: 16108legalized: true109regBankSelected: true110registers:111 - { id: 0, class: vecr }112 - { id: 1, class: vecr }113 - { id: 2, class: vecr }114# AVX2: %2:vr256 = VPSUBQYrr %0, %1115#116# AVX512VL: %2:vr256x = VPSUBQZ256rr %0, %1117#118# AVX512BWVL: %2:vr256x = VPSUBQZ256rr %0, %1119body: |120 bb.1 (%ir-block.0):121 liveins: $ymm0, $ymm1122 123 %0(<4 x s64>) = COPY $ymm0124 %1(<4 x s64>) = COPY $ymm1125 %2(<4 x s64>) = G_SUB %0, %1126 $ymm0 = COPY %2(<4 x s64>)127 RET 0, implicit $ymm0128 129...130