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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL3 4--- |5 define <64 x i8> @test_sub_v64i8(<64 x i8> %arg1, <64 x i8> %arg2) #0 {6 %ret = sub <64 x i8> %arg1, %arg27 ret <64 x i8> %ret8 }9 10 define <32 x i16> @test_sub_v32i16(<32 x i16> %arg1, <32 x i16> %arg2) #0 {11 %ret = sub <32 x i16> %arg1, %arg212 ret <32 x i16> %ret13 }14 15 define <16 x i32> @test_sub_v16i32(<16 x i32> %arg1, <16 x i32> %arg2) #1 {16 %ret = sub <16 x i32> %arg1, %arg217 ret <16 x i32> %ret18 }19 20 define <8 x i64> @test_sub_v8i64(<8 x i64> %arg1, <8 x i64> %arg2) #1 {21 %ret = sub <8 x i64> %arg1, %arg222 ret <8 x i64> %ret23 }24 25 attributes #0 = { "target-features"="+avx512f,+avx512bw" }26 attributes #1 = { "target-features"="+avx512f" }27...28---29name: test_sub_v64i830alignment: 1631legalized: true32regBankSelected: true33registers:34 - { id: 0, class: vecr }35 - { id: 1, class: vecr }36 - { id: 2, class: vecr }37body: |38 bb.1 (%ir-block.0):39 liveins: $zmm0, $zmm140 41 ; ALL-LABEL: name: test_sub_v64i842 ; ALL: [[COPY:%[0-9]+]]:vr512 = COPY $zmm043 ; ALL: [[COPY1:%[0-9]+]]:vr512 = COPY $zmm144 ; ALL: [[VPSUBBZrr:%[0-9]+]]:vr512 = VPSUBBZrr [[COPY]], [[COPY1]]45 ; ALL: $zmm0 = COPY [[VPSUBBZrr]]46 ; ALL: RET 0, implicit $zmm047 %0(<64 x s8>) = COPY $zmm048 %1(<64 x s8>) = COPY $zmm149 %2(<64 x s8>) = G_SUB %0, %150 $zmm0 = COPY %2(<64 x s8>)51 RET 0, implicit $zmm052 53...54---55name: test_sub_v32i1656alignment: 1657legalized: true58regBankSelected: true59registers:60 - { id: 0, class: vecr }61 - { id: 1, class: vecr }62 - { id: 2, class: vecr }63body: |64 bb.1 (%ir-block.0):65 liveins: $zmm0, $zmm166 67 ; ALL-LABEL: name: test_sub_v32i1668 ; ALL: [[COPY:%[0-9]+]]:vr512 = COPY $zmm069 ; ALL: [[COPY1:%[0-9]+]]:vr512 = COPY $zmm170 ; ALL: [[VPSUBWZrr:%[0-9]+]]:vr512 = VPSUBWZrr [[COPY]], [[COPY1]]71 ; ALL: $zmm0 = COPY [[VPSUBWZrr]]72 ; ALL: RET 0, implicit $zmm073 %0(<32 x s16>) = COPY $zmm074 %1(<32 x s16>) = COPY $zmm175 %2(<32 x s16>) = G_SUB %0, %176 $zmm0 = COPY %2(<32 x s16>)77 RET 0, implicit $zmm078 79...80---81name: test_sub_v16i3282alignment: 1683legalized: true84regBankSelected: true85registers:86 - { id: 0, class: vecr }87 - { id: 1, class: vecr }88 - { id: 2, class: vecr }89body: |90 bb.1 (%ir-block.0):91 liveins: $zmm0, $zmm192 93 ; ALL-LABEL: name: test_sub_v16i3294 ; ALL: [[COPY:%[0-9]+]]:vr512 = COPY $zmm095 ; ALL: [[COPY1:%[0-9]+]]:vr512 = COPY $zmm196 ; ALL: [[VPSUBDZrr:%[0-9]+]]:vr512 = VPSUBDZrr [[COPY]], [[COPY1]]97 ; ALL: $zmm0 = COPY [[VPSUBDZrr]]98 ; ALL: RET 0, implicit $zmm099 %0(<16 x s32>) = COPY $zmm0100 %1(<16 x s32>) = COPY $zmm1101 %2(<16 x s32>) = G_SUB %0, %1102 $zmm0 = COPY %2(<16 x s32>)103 RET 0, implicit $zmm0104 105...106---107name: test_sub_v8i64108alignment: 16109legalized: true110regBankSelected: true111registers:112 - { id: 0, class: vecr }113 - { id: 1, class: vecr }114 - { id: 2, class: vecr }115body: |116 bb.1 (%ir-block.0):117 liveins: $zmm0, $zmm1118 119 ; ALL-LABEL: name: test_sub_v8i64120 ; ALL: [[COPY:%[0-9]+]]:vr512 = COPY $zmm0121 ; ALL: [[COPY1:%[0-9]+]]:vr512 = COPY $zmm1122 ; ALL: [[VPSUBQZrr:%[0-9]+]]:vr512 = VPSUBQZrr [[COPY]], [[COPY1]]123 ; ALL: $zmm0 = COPY [[VPSUBQZrr]]124 ; ALL: RET 0, implicit $zmm0125 %0(<8 x s64>) = COPY $zmm0126 %1(<8 x s64>) = COPY $zmm1127 %2(<8 x s64>) = G_SUB %0, %1128 $zmm0 = COPY %2(<8 x s64>)129 RET 0, implicit $zmm0130 131...132