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1# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=ALL,NO_AVX512VL,SSE2# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=ALL,NO_AVX512VL,AVX3# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=ALL,NO_AVX512VL,AVX512F4# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -mattr=+avx512vl -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=ALL,AVX512VL5 6--- |7 define i64 @test_sub_i64(i64 %arg1, i64 %arg2) {8 %ret = sub i64 %arg1, %arg29 ret i64 %ret10 }11 12 define i32 @test_sub_i32(i32 %arg1, i32 %arg2) {13 %ret = sub i32 %arg1, %arg214 ret i32 %ret15 }16 17 define <4 x i32> @test_sub_v4i32(<4 x i32> %arg1, <4 x i32> %arg2) {18 %ret = sub <4 x i32> %arg1, %arg219 ret <4 x i32> %ret20 }21 22 define <4 x float> @test_sub_v4f32(<4 x float> %arg1, <4 x float> %arg2) {23 %ret = fsub <4 x float> %arg1, %arg224 ret <4 x float> %ret25 }26 27...28---29name: test_sub_i6430legalized: true31regBankSelected: true32registers:33 - { id: 0, class: gpr }34 - { id: 1, class: gpr }35 - { id: 2, class: gpr }36# ALL: %0:gr64 = COPY $rdi37# ALL-NEXT: %1:gr64 = COPY $rsi38# ALL-NEXT: %2:gr64 = SUB64rr %0, %139body: |40 bb.1 (%ir-block.0):41 liveins: $edi, $esi42 43 %0(s64) = COPY $rdi44 %1(s64) = COPY $rsi45 %2(s64) = G_SUB %0, %146 $rax = COPY %2(s64)47 48...49 50---51name: test_sub_i3252legalized: true53regBankSelected: true54registers:55 - { id: 0, class: gpr }56 - { id: 1, class: gpr }57 - { id: 2, class: gpr }58# ALL: %0:gr32 = COPY $edi59# ALL-NEXT: %1:gr32 = COPY $esi60# ALL-NEXT: %2:gr32 = SUB32rr %0, %161body: |62 bb.1 (%ir-block.0):63 liveins: $edi, $esi64 65 %0(s32) = COPY $edi66 %1(s32) = COPY $esi67 %2(s32) = G_SUB %0, %168 $eax = COPY %2(s32)69 70...71---72name: test_sub_v4i3273alignment: 1674legalized: true75regBankSelected: true76selected: false77tracksRegLiveness: true78registers:79 - { id: 0, class: vecr }80 - { id: 1, class: vecr }81 - { id: 2, class: vecr }82# NO_AVX512VL: %0:vr128 = COPY $xmm083# AVX512VL: %0:vr128x = COPY $xmm084# NO_AVX512VL: %1:vr128 = COPY $xmm185# AVX512VL: %1:vr128x = COPY $xmm186# SSE-NEXT: %2:vr128 = PSUBDrr %0, %187# AVX-NEXT: %2:vr128 = VPSUBDrr %0, %188# AVX512F-NEXT: %2:vr128 = VPSUBDrr %0, %189# AVX512VL-NEXT: %2:vr128x = VPSUBDZ128rr %0, %190body: |91 bb.1 (%ir-block.0):92 liveins: $xmm0, $xmm193 94 %0(<4 x s32>) = COPY $xmm095 %1(<4 x s32>) = COPY $xmm196 %2(<4 x s32>) = G_SUB %0, %197 $xmm0 = COPY %2(<4 x s32>)98 RET 0, implicit $xmm099 100...101---102name: test_sub_v4f32103alignment: 16104legalized: true105regBankSelected: true106selected: false107tracksRegLiveness: true108registers:109 - { id: 0, class: vecr }110 - { id: 1, class: vecr }111 - { id: 2, class: vecr }112# NO_AVX512VL: %0:vr128 = COPY $xmm0113# NO_AVX512VL: %1:vr128 = COPY $xmm1114# SSE-NEXT: %2:vr128 = nofpexcept SUBPSrr %0, %1115# AVX-NEXT: %2:vr128 = nofpexcept VSUBPSrr %0, %1116# AVX512F-NEXT: %2:vr128 = nofpexcept VSUBPSrr %0, %1117#118# AVX512VL: %0:vr128x = COPY $xmm0119# AVX512VL: %1:vr128x = COPY $xmm1120# AVX512VL-NEXT: %2:vr128x = nofpexcept VSUBPSZ128rr %0, %1121body: |122 bb.1 (%ir-block.0):123 liveins: $xmm0, $xmm1124 125 %0(<4 x s32>) = COPY $xmm0126 %1(<4 x s32>) = COPY $xmm1127 %2(<4 x s32>) = G_FSUB %0, %1128 $xmm0 = COPY %2(<4 x s32>)129 RET 0, implicit $xmm0130 131...132