65 lines · plain
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL3--- |4 define void @test_unmerge_v128() {5 ret void6 }7 8 define void @test_unmerge_v256() {9 ret void10 }11 12...13---14name: test_unmerge_v12815alignment: 1616legalized: true17regBankSelected: true18registers:19 - { id: 0, class: vecr }20 - { id: 1, class: vecr }21 - { id: 2, class: vecr }22 - { id: 3, class: vecr }23 - { id: 4, class: vecr }24body: |25 bb.1 (%ir-block.0):26 27 ; ALL-LABEL: name: test_unmerge_v12828 ; ALL: [[DEF:%[0-9]+]]:vr512 = IMPLICIT_DEF29 ; ALL: [[COPY:%[0-9]+]]:vr128x = COPY [[DEF]].sub_xmm30 ; ALL: [[VEXTRACTF32X4Zrri:%[0-9]+]]:vr128x = VEXTRACTF32X4Zrri [[DEF]], 131 ; ALL: [[VEXTRACTF32X4Zrri1:%[0-9]+]]:vr128x = VEXTRACTF32X4Zrri [[DEF]], 232 ; ALL: [[VEXTRACTF32X4Zrri2:%[0-9]+]]:vr128x = VEXTRACTF32X4Zrri [[DEF]], 333 ; ALL: $xmm0 = COPY [[COPY]]34 ; ALL: RET 0, implicit $xmm035 %0(<16 x s32>) = IMPLICIT_DEF36 %1(<4 x s32>), %2(<4 x s32>), %3(<4 x s32>), %4(<4 x s32>) = G_UNMERGE_VALUES %0(<16 x s32>)37 $xmm0 = COPY %1(<4 x s32>)38 RET 0, implicit $xmm039 40...41---42name: test_unmerge_v25643alignment: 1644legalized: true45regBankSelected: true46registers:47 - { id: 0, class: vecr }48 - { id: 1, class: vecr }49 - { id: 2, class: vecr }50body: |51 bb.1 (%ir-block.0):52 53 ; ALL-LABEL: name: test_unmerge_v25654 ; ALL: [[DEF:%[0-9]+]]:vr512 = IMPLICIT_DEF55 ; ALL: [[COPY:%[0-9]+]]:vr256x = COPY [[DEF]].sub_ymm56 ; ALL: [[VEXTRACTF64X4Zrri:%[0-9]+]]:vr256x = VEXTRACTF64X4Zrri [[DEF]], 157 ; ALL: $ymm0 = COPY [[COPY]]58 ; ALL: RET 0, implicit $ymm059 %0(<16 x s32>) = IMPLICIT_DEF60 %1(<8 x s32>), %2(<8 x s32>) = G_UNMERGE_VALUES %0(<16 x s32>)61 $ymm0 = COPY %1(<8 x s32>)62 RET 0, implicit $ymm063 64...65