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1; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2; RUN: llc -mtriple=x86_64-linux-gnu -O0 -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - 2>&1 | FileCheck %s3 4define i8 @zext_i1_to_i8(i1 %val) {5 ; CHECK-LABEL: name: zext_i1_to_i86 ; CHECK: bb.1 (%ir-block.0):7 ; CHECK: liveins: $edi8 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi9 ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s32)10 ; CHECK: [[ZEXT:%[0-9]+]]:_(s8) = G_ZEXT [[TRUNC]](s1)11 ; CHECK: $al = COPY [[ZEXT]](s8)12 ; CHECK: RET 0, implicit $al13 %res = zext i1 %val to i814 ret i8 %res15}16 17define i16 @zext_i1_to_i16(i1 %val) {18 ; CHECK-LABEL: name: zext_i1_to_i1619 ; CHECK: bb.1 (%ir-block.0):20 ; CHECK: liveins: $edi21 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi22 ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s32)23 ; CHECK: [[ZEXT:%[0-9]+]]:_(s16) = G_ZEXT [[TRUNC]](s1)24 ; CHECK: $ax = COPY [[ZEXT]](s16)25 ; CHECK: RET 0, implicit $ax26 %res = zext i1 %val to i1627 ret i16 %res28}29 30define i32 @zext_i1_to_i32(i1 %val) {31 ; CHECK-LABEL: name: zext_i1_to_i3232 ; CHECK: bb.1 (%ir-block.0):33 ; CHECK: liveins: $edi34 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi35 ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s32)36 ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC]](s1)37 ; CHECK: $eax = COPY [[ZEXT]](s32)38 ; CHECK: RET 0, implicit $eax39 %res = zext i1 %val to i3240 ret i32 %res41}42 43define i64 @zext_i1_to_i64(i1 %val) {44 ; CHECK-LABEL: name: zext_i1_to_i6445 ; CHECK: bb.1 (%ir-block.0):46 ; CHECK: liveins: $edi47 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi48 ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s32)49 ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[TRUNC]](s1)50 ; CHECK: $rax = COPY [[ZEXT]](s64)51 ; CHECK: RET 0, implicit $rax52 %res = zext i1 %val to i6453 ret i64 %res54}55 56define i16 @zext_i8_to_i16(i8 %val) {57 ; CHECK-LABEL: name: zext_i8_to_i1658 ; CHECK: bb.1 (%ir-block.0):59 ; CHECK: liveins: $edi60 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi61 ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)62 ; CHECK: [[ZEXT:%[0-9]+]]:_(s16) = G_ZEXT [[TRUNC]](s8)63 ; CHECK: $ax = COPY [[ZEXT]](s16)64 ; CHECK: RET 0, implicit $ax65 %res = zext i8 %val to i1666 ret i16 %res67}68 69define i32 @zext_i8_to_i32(i8 %val) {70 ; CHECK-LABEL: name: zext_i8_to_i3271 ; CHECK: bb.1 (%ir-block.0):72 ; CHECK: liveins: $edi73 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi74 ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)75 ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC]](s8)76 ; CHECK: $eax = COPY [[ZEXT]](s32)77 ; CHECK: RET 0, implicit $eax78 %res = zext i8 %val to i3279 ret i32 %res80}81 82define i64 @zext_i8_to_i64(i8 %val) {83 ; CHECK-LABEL: name: zext_i8_to_i6484 ; CHECK: bb.1 (%ir-block.0):85 ; CHECK: liveins: $edi86 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi87 ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)88 ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[TRUNC]](s8)89 ; CHECK: $rax = COPY [[ZEXT]](s64)90 ; CHECK: RET 0, implicit $rax91 %res = zext i8 %val to i6492 ret i64 %res93}94 95define i32 @zext_i16_to_i32(i16 %val) {96 ; CHECK-LABEL: name: zext_i16_to_i3297 ; CHECK: bb.1 (%ir-block.0):98 ; CHECK: liveins: $edi99 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi100 ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)101 ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC]](s16)102 ; CHECK: $eax = COPY [[ZEXT]](s32)103 ; CHECK: RET 0, implicit $eax104 %res = zext i16 %val to i32105 ret i32 %res106}107 108define i64 @zext_i16_to_i64(i16 %val) {109 ; CHECK-LABEL: name: zext_i16_to_i64110 ; CHECK: bb.1 (%ir-block.0):111 ; CHECK: liveins: $edi112 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi113 ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)114 ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[TRUNC]](s16)115 ; CHECK: $rax = COPY [[ZEXT]](s64)116 ; CHECK: RET 0, implicit $rax117 %res = zext i16 %val to i64118 ret i64 %res119}120 121define i64 @zext_i32_to_i64(i32 %val) {122 ; CHECK-LABEL: name: zext_i32_to_i64123 ; CHECK: bb.1 (%ir-block.0):124 ; CHECK: liveins: $edi125 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi126 ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY]](s32)127 ; CHECK: $rax = COPY [[ZEXT]](s64)128 ; CHECK: RET 0, implicit $rax129 %res = zext i32 %val to i64130 ret i64 %res131}132 133define i8 @test_sdiv_i8(i8 %arg1, i8 %arg2) {134 ; CHECK-LABEL: name: test_sdiv_i8135 ; CHECK: bb.1 (%ir-block.0):136 ; CHECK: liveins: $edi, $esi137 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi138 ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)139 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $esi140 ; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s32)141 ; CHECK: [[SDIV:%[0-9]+]]:_(s8) = G_SDIV [[TRUNC]], [[TRUNC1]]142 ; CHECK: $al = COPY [[SDIV]](s8)143 ; CHECK: RET 0, implicit $al144 %res = sdiv i8 %arg1, %arg2145 ret i8 %res146}147 148define i16 @test_sdiv_i16(i16 %arg1, i16 %arg2) {149 ; CHECK-LABEL: name: test_sdiv_i16150 ; CHECK: bb.1 (%ir-block.0):151 ; CHECK: liveins: $edi, $esi152 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi153 ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)154 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $esi155 ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)156 ; CHECK: [[SDIV:%[0-9]+]]:_(s16) = G_SDIV [[TRUNC]], [[TRUNC1]]157 ; CHECK: $ax = COPY [[SDIV]](s16)158 ; CHECK: RET 0, implicit $ax159 %res = sdiv i16 %arg1, %arg2160 ret i16 %res161}162 163define i32 @test_sdiv_i32(i32 %arg1, i32 %arg2) {164 ; CHECK-LABEL: name: test_sdiv_i32165 ; CHECK: bb.1 (%ir-block.0):166 ; CHECK: liveins: $edi, $esi167 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi168 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $esi169 ; CHECK: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[COPY]], [[COPY1]]170 ; CHECK: $eax = COPY [[SDIV]](s32)171 ; CHECK: RET 0, implicit $eax172 %res = sdiv i32 %arg1, %arg2173 ret i32 %res174}175 176define i64 @test_sdiv_i64(i64 %arg1, i64 %arg2) {177 ; CHECK-LABEL: name: test_sdiv_i64178 ; CHECK: bb.1 (%ir-block.0):179 ; CHECK: liveins: $rdi, $rsi180 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $rdi181 ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $rsi182 ; CHECK: [[SDIV:%[0-9]+]]:_(s64) = G_SDIV [[COPY]], [[COPY1]]183 ; CHECK: $rax = COPY [[SDIV]](s64)184 ; CHECK: RET 0, implicit $rax185 %res = sdiv i64 %arg1, %arg2186 ret i64 %res187}188define float @test_fptrunc(double %in) {189 ; CHECK-LABEL: name: test_fptrunc190 ; CHECK: bb.1 (%ir-block.0):191 ; CHECK: liveins: $xmm0192 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $xmm0193 ; CHECK: [[FPTRUNC:%[0-9]+]]:_(s32) = G_FPTRUNC [[COPY]](s64)194 ; CHECK: $xmm0 = COPY [[FPTRUNC]](s32)195 ; CHECK: RET 0, implicit $xmm0196 %res = fptrunc double %in to float197 ret float %res198}199 200define i8 @test_srem_i8(i8 %arg1, i8 %arg2) {201 ; CHECK-LABEL: name: test_srem_i8202 ; CHECK: bb.1 (%ir-block.0):203 ; CHECK: liveins: $edi, $esi204 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi205 ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)206 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $esi207 ; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s32)208 ; CHECK: [[SREM:%[0-9]+]]:_(s8) = G_SREM [[TRUNC]], [[TRUNC1]]209 ; CHECK: $al = COPY [[SREM]](s8)210 ; CHECK: RET 0, implicit $al211 %res = srem i8 %arg1, %arg2212 ret i8 %res213}214 215define i16 @test_srem_i16(i16 %arg1, i16 %arg2) {216 ; CHECK-LABEL: name: test_srem_i16217 ; CHECK: bb.1 (%ir-block.0):218 ; CHECK: liveins: $edi, $esi219 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi220 ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)221 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $esi222 ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)223 ; CHECK: [[SREM:%[0-9]+]]:_(s16) = G_SREM [[TRUNC]], [[TRUNC1]]224 ; CHECK: $ax = COPY [[SREM]](s16)225 ; CHECK: RET 0, implicit $ax226 %res = srem i16 %arg1, %arg2227 ret i16 %res228}229 230define i32 @test_srem_i32(i32 %arg1, i32 %arg2) {231 ; CHECK-LABEL: name: test_srem_i32232 ; CHECK: bb.1 (%ir-block.0):233 ; CHECK: liveins: $edi, $esi234 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi235 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $esi236 ; CHECK: [[SREM:%[0-9]+]]:_(s32) = G_SREM [[COPY]], [[COPY1]]237 ; CHECK: $eax = COPY [[SREM]](s32)238 ; CHECK: RET 0, implicit $eax239 %res = srem i32 %arg1, %arg2240 ret i32 %res241}242 243define i64 @test_srem_i64(i64 %arg1, i64 %arg2) {244 ; CHECK-LABEL: name: test_srem_i64245 ; CHECK: bb.1 (%ir-block.0):246 ; CHECK: liveins: $rdi, $rsi247 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $rdi248 ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $rsi249 ; CHECK: [[SREM:%[0-9]+]]:_(s64) = G_SREM [[COPY]], [[COPY1]]250 ; CHECK: $rax = COPY [[SREM]](s64)251 ; CHECK: RET 0, implicit $rax252 %res = srem i64 %arg1, %arg2253 ret i64 %res254}255 256define i8 @test_udiv_i8(i8 %arg1, i8 %arg2) {257 ; CHECK-LABEL: name: test_udiv_i8258 ; CHECK: bb.1 (%ir-block.0):259 ; CHECK: liveins: $edi, $esi260 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi261 ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)262 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $esi263 ; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s32)264 ; CHECK: [[UDIV:%[0-9]+]]:_(s8) = G_UDIV [[TRUNC]], [[TRUNC1]]265 ; CHECK: $al = COPY [[UDIV]](s8)266 ; CHECK: RET 0, implicit $al267 %res = udiv i8 %arg1, %arg2268 ret i8 %res269}270 271define i16 @test_udiv_i16(i16 %arg1, i16 %arg2) {272 ; CHECK-LABEL: name: test_udiv_i16273 ; CHECK: bb.1 (%ir-block.0):274 ; CHECK: liveins: $edi, $esi275 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi276 ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)277 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $esi278 ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)279 ; CHECK: [[UDIV:%[0-9]+]]:_(s16) = G_UDIV [[TRUNC]], [[TRUNC1]]280 ; CHECK: $ax = COPY [[UDIV]](s16)281 ; CHECK: RET 0, implicit $ax282 %res = udiv i16 %arg1, %arg2283 ret i16 %res284}285 286define i32 @test_udiv_i32(i32 %arg1, i32 %arg2) {287 ; CHECK-LABEL: name: test_udiv_i32288 ; CHECK: bb.1 (%ir-block.0):289 ; CHECK: liveins: $edi, $esi290 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi291 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $esi292 ; CHECK: [[UDIV:%[0-9]+]]:_(s32) = G_UDIV [[COPY]], [[COPY1]]293 ; CHECK: $eax = COPY [[UDIV]](s32)294 ; CHECK: RET 0, implicit $eax295 %res = udiv i32 %arg1, %arg2296 ret i32 %res297}298 299define i64 @test_udiv_i64(i64 %arg1, i64 %arg2) {300 ; CHECK-LABEL: name: test_udiv_i64301 ; CHECK: bb.1 (%ir-block.0):302 ; CHECK: liveins: $rdi, $rsi303 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $rdi304 ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $rsi305 ; CHECK: [[UDIV:%[0-9]+]]:_(s64) = G_UDIV [[COPY]], [[COPY1]]306 ; CHECK: $rax = COPY [[UDIV]](s64)307 ; CHECK: RET 0, implicit $rax308 %res = udiv i64 %arg1, %arg2309 ret i64 %res310}311 312define i8 @test_urem_i8(i8 %arg1, i8 %arg2) {313 ; CHECK-LABEL: name: test_urem_i8314 ; CHECK: bb.1 (%ir-block.0):315 ; CHECK: liveins: $edi, $esi316 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi317 ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)318 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $esi319 ; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s32)320 ; CHECK: [[UREM:%[0-9]+]]:_(s8) = G_UREM [[TRUNC]], [[TRUNC1]]321 ; CHECK: $al = COPY [[UREM]](s8)322 ; CHECK: RET 0, implicit $al323 %res = urem i8 %arg1, %arg2324 ret i8 %res325}326 327define i16 @test_urem_i16(i16 %arg1, i16 %arg2) {328 ; CHECK-LABEL: name: test_urem_i16329 ; CHECK: bb.1 (%ir-block.0):330 ; CHECK: liveins: $edi, $esi331 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi332 ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)333 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $esi334 ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)335 ; CHECK: [[UREM:%[0-9]+]]:_(s16) = G_UREM [[TRUNC]], [[TRUNC1]]336 ; CHECK: $ax = COPY [[UREM]](s16)337 ; CHECK: RET 0, implicit $ax338 %res = urem i16 %arg1, %arg2339 ret i16 %res340}341 342define i32 @test_urem_i32(i32 %arg1, i32 %arg2) {343 ; CHECK-LABEL: name: test_urem_i32344 ; CHECK: bb.1 (%ir-block.0):345 ; CHECK: liveins: $edi, $esi346 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi347 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $esi348 ; CHECK: [[UREM:%[0-9]+]]:_(s32) = G_UREM [[COPY]], [[COPY1]]349 ; CHECK: $eax = COPY [[UREM]](s32)350 ; CHECK: RET 0, implicit $eax351 %res = urem i32 %arg1, %arg2352 ret i32 %res353}354 355define i64 @test_urem_i64(i64 %arg1, i64 %arg2) {356 ; CHECK-LABEL: name: test_urem_i64357 ; CHECK: bb.1 (%ir-block.0):358 ; CHECK: liveins: $rdi, $rsi359 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $rdi360 ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $rsi361 ; CHECK: [[UREM:%[0-9]+]]:_(s64) = G_UREM [[COPY]], [[COPY1]]362 ; CHECK: $rax = COPY [[UREM]](s64)363 ; CHECK: RET 0, implicit $rax364 %res = urem i64 %arg1, %arg2365 ret i64 %res366}367 368define <2 x float> @test_const_v2f32() {369 ; CHECK-LABEL: name: test_const_v2f32370 ; CHECK: bb.1 (%ir-block.0):371 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00372 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32)373 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<2 x s32>)374 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF375 ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[DEF]](s32), [[DEF]](s32)376 ; CHECK-NEXT: $xmm0 = COPY [[BUILD_VECTOR1]](<4 x s32>)377 ; CHECK-NEXT: RET 0, implicit $xmm0378 ret <2 x float> <float 1.0, float 1.0>379}380 381define <3 x float> @test_const_v3f32() {382 ; CHECK-LABEL: name: test_const_v3f32383 ; CHECK: bb.1 (%ir-block.0):384 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00385 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32)386 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<3 x s32>)387 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF388 ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[UV2]](s32), [[DEF]](s32)389 ; CHECK-NEXT: $xmm0 = COPY [[BUILD_VECTOR1]](<4 x s32>)390 ; CHECK-NEXT: RET 0, implicit $xmm0391 ret <3 x float> <float 1.0, float 1.0, float 1.0>392}393 394define <5 x float> @test_const_v5f32() {395 ; CHECK-LABEL: name: test_const_v5f32396 ; CHECK: bb.1 (%ir-block.0):397 ; CHECK-NEXT: liveins: $rdi398 ; CHECK-NEXT: {{ $}}399 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $rdi400 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00401 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<5 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)402 ; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<5 x s32>), [[COPY]](p0) :: (store (<5 x s32>), align 32)403 ; CHECK-NEXT: $rax = COPY [[COPY]](p0)404 ; CHECK-NEXT: RET 0405 ret <5 x float> <float 1.0, float 1.0, float 1.0, float 1.0, float 1.0>406}407 408define <6 x float> @test_const_v6f32() {409 ; CHECK-LABEL: name: test_const_v6f32410 ; CHECK: bb.1 (%ir-block.0):411 ; CHECK-NEXT: liveins: $rdi412 ; CHECK-NEXT: {{ $}}413 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $rdi414 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00415 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<6 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)416 ; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<6 x s32>), [[COPY]](p0) :: (store (<6 x s32>), align 32)417 ; CHECK-NEXT: $rax = COPY [[COPY]](p0)418 ; CHECK-NEXT: RET 0419 ret <6 x float> <float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0>420}421